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Highly Reliable Non-volatile Logic Circuit Technology and Its Application
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A ferroelectric-based (FE-based) non-volatile logic is proposed for low-power LSI. Standby currents in a logic circuit can be cut off by using FE-based non-volatile flip-flops (NVFFs), and the standby power can be reduced to zero. The FE capacitor is accessed only when the power turns on/off, performance of the NVFF is almost as same as that of the conventional flip-flop (FF) in a logic operation. The use of complementarily stored data in coupled FE capacitors makes it possible to realize wide read voltage margin, which guarantees 10 years retention at 85 degree Celsius under less than 1.5V operation. The low supply voltage and electro-static discharge (ESD) detection technique prevents data destruction caused by illegal access for the FE capacitor during standby state. Applying the proposed circuitry in CPU, the write and read operation for all FE capacitors in 1.6k-bit NVFFs are performed within 7µs and 3µs with access energy of 23.1nJ and 8.1nJ, respectively, using 130nm CMOS with Pb(Zr,Ti)O3(PZT) thin films.
- Publication
- IEICE TRANSACTIONS on Information Vol.E97-D No.9 pp.2226-2233
- Publication Date
- 2014/09/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2013LOP0017
- Type of Manuscript
- Special Section INVITED PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
- Category
Authors
Hiromitsu KIMURA
ROHM Co., Ltd.
Zhiyong ZHONG
ROHM Co., Ltd.
Yuta MIZUOCHI
ROHM Co., Ltd.
Norihiro KINOUCHI
ROHM Co., Ltd.
Yoshinobu ICHIDA
ROHM Co., Ltd.
Yoshikazu FUJIMORI
ROHM Co., Ltd.
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Hiromitsu KIMURA, Zhiyong ZHONG, Yuta MIZUOCHI, Norihiro KINOUCHI, Yoshinobu ICHIDA, Yoshikazu FUJIMORI, "Highly Reliable Non-volatile Logic Circuit Technology and Its Application" in IEICE TRANSACTIONS on Information,
vol. E97-D, no. 9, pp. 2226-2233, September 2014, doi: 10.1587/transinf.2013LOP0017.
Abstract: A ferroelectric-based (FE-based) non-volatile logic is proposed for low-power LSI. Standby currents in a logic circuit can be cut off by using FE-based non-volatile flip-flops (NVFFs), and the standby power can be reduced to zero. The FE capacitor is accessed only when the power turns on/off, performance of the NVFF is almost as same as that of the conventional flip-flop (FF) in a logic operation. The use of complementarily stored data in coupled FE capacitors makes it possible to realize wide read voltage margin, which guarantees 10 years retention at 85 degree Celsius under less than 1.5V operation. The low supply voltage and electro-static discharge (ESD) detection technique prevents data destruction caused by illegal access for the FE capacitor during standby state. Applying the proposed circuitry in CPU, the write and read operation for all FE capacitors in 1.6k-bit NVFFs are performed within 7µs and 3µs with access energy of 23.1nJ and 8.1nJ, respectively, using 130nm CMOS with Pb(Zr,Ti)O3(PZT) thin films.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2013LOP0017/_p
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@ARTICLE{e97-d_9_2226,
author={Hiromitsu KIMURA, Zhiyong ZHONG, Yuta MIZUOCHI, Norihiro KINOUCHI, Yoshinobu ICHIDA, Yoshikazu FUJIMORI, },
journal={IEICE TRANSACTIONS on Information},
title={Highly Reliable Non-volatile Logic Circuit Technology and Its Application},
year={2014},
volume={E97-D},
number={9},
pages={2226-2233},
abstract={A ferroelectric-based (FE-based) non-volatile logic is proposed for low-power LSI. Standby currents in a logic circuit can be cut off by using FE-based non-volatile flip-flops (NVFFs), and the standby power can be reduced to zero. The FE capacitor is accessed only when the power turns on/off, performance of the NVFF is almost as same as that of the conventional flip-flop (FF) in a logic operation. The use of complementarily stored data in coupled FE capacitors makes it possible to realize wide read voltage margin, which guarantees 10 years retention at 85 degree Celsius under less than 1.5V operation. The low supply voltage and electro-static discharge (ESD) detection technique prevents data destruction caused by illegal access for the FE capacitor during standby state. Applying the proposed circuitry in CPU, the write and read operation for all FE capacitors in 1.6k-bit NVFFs are performed within 7µs and 3µs with access energy of 23.1nJ and 8.1nJ, respectively, using 130nm CMOS with Pb(Zr,Ti)O3(PZT) thin films.},
keywords={},
doi={10.1587/transinf.2013LOP0017},
ISSN={1745-1361},
month={September},}
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TY - JOUR
TI - Highly Reliable Non-volatile Logic Circuit Technology and Its Application
T2 - IEICE TRANSACTIONS on Information
SP - 2226
EP - 2233
AU - Hiromitsu KIMURA
AU - Zhiyong ZHONG
AU - Yuta MIZUOCHI
AU - Norihiro KINOUCHI
AU - Yoshinobu ICHIDA
AU - Yoshikazu FUJIMORI
PY - 2014
DO - 10.1587/transinf.2013LOP0017
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E97-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 2014
AB - A ferroelectric-based (FE-based) non-volatile logic is proposed for low-power LSI. Standby currents in a logic circuit can be cut off by using FE-based non-volatile flip-flops (NVFFs), and the standby power can be reduced to zero. The FE capacitor is accessed only when the power turns on/off, performance of the NVFF is almost as same as that of the conventional flip-flop (FF) in a logic operation. The use of complementarily stored data in coupled FE capacitors makes it possible to realize wide read voltage margin, which guarantees 10 years retention at 85 degree Celsius under less than 1.5V operation. The low supply voltage and electro-static discharge (ESD) detection technique prevents data destruction caused by illegal access for the FE capacitor during standby state. Applying the proposed circuitry in CPU, the write and read operation for all FE capacitors in 1.6k-bit NVFFs are performed within 7µs and 3µs with access energy of 23.1nJ and 8.1nJ, respectively, using 130nm CMOS with Pb(Zr,Ti)O3(PZT) thin films.
ER -
English
