Recently, the Services Oriented Architectures (SOA) have been recognized as the key to the integration and interoperability of different applications and systems that coexist in an organization. However, even though the use of SOA has increased, some applications are unable to use it. That is the case of mission critical information applications, whose requirements such as high reliability, non-stop operation, high flexibility and high performance are not satisfied by conventional SOA infrastructures. In this article we present a novel approach of combining SOA with Autonomous Decentralized Systems (ADS) in order to provide an infrastructure that can satisfy those requirements. We have named this infrastructure Autonomous Decentralized Service Oriented Architecture (ADSOA). We present the concept and architecture of ADSOA, as well as the Loosely Couple Delivery Transaction and Synchronization Technology for assuring the data consistency and high reliability of the application. Moreover, a real implementation and evaluation of the proposal in a mission critical information system, the Uniqueness Verifying Public Key Infrastructure (UV-PKI), is shown in order to prove its effectiveness.

A ferroelectric-based (FE-based) non-volatile logic is proposed for low-power LSI. Standby currents in a logic circuit can be cut off by using FE-based non-volatile flip-flops (NVFFs), and the standby power can be reduced to zero. The FE capacitor is accessed only when the power turns on/off, performance of the NVFF is almost as same as that of the conventional flip-flop (FF) in a logic operation. The use of complementarily stored data in coupled FE capacitors makes it possible to realize wide read voltage margin, which guarantees 10 years retention at 85 degree Celsius under less than 1.5V operation. The low supply voltage and electro-static discharge (ESD) detection technique prevents data destruction caused by illegal access for the FE capacitor during standby state. Applying the proposed circuitry in CPU, the write and read operation for all FE capacitors in 1.6k-bit NVFFs are performed within 7µs and 3µs with access energy of 23.1nJ and 8.1nJ, respectively, using 130nm CMOS with Pb(Zr,Ti)O3(PZT) thin films.

We have proposed Rate-based Multi-path Transmission Control Protocol (R-M/TCP) for improving reliability and performance of data transfer over the Internet by using multiple paths. Congestion control in R-M/TCP is performed in a rate-based and loss-avoidance manner. It attempts to estimate the available bandwidth and the queue length of the used routes in order to fully utilize the bandwidth resources. However, it has been reported that when the used routes' characteristics, i.e. available bandwidth and delay, are much different, R-M/TCP cannot achieve the desired throughput from the routes. This is because R-M/TCP originally transmits data packets in a round-robin manner through the routes. In this paper, therefore, we propose R-M/TCP using Packet Scheduling Algorithm (PSA). Instead of using the round-robin manner, R-M/TCP utilizes PSA that accounts for time-varying bandwidth and delay of each path so that number of data packets arriving in out-of-order at the receiver can be minimized and the desired throughput can be achieved. Quantitative simulations are conducted to show effectiveness of R-M/TCP using PSA.

There is "Processing speed improvement of the automatic fare collection gate (AFC gate)" as one of the important problems to correspond to the passengers getting on and off in high density transportation at the peak. On the other hand, reliability is indispensable to handle the ticket that is the note. Therefore, the ticket system that has both high-speed processing and high reliability is necessary and indispensable. For the passenger's convenience improvement and maintenance cost reduction, wireless IC card ticket system is hoped. However, the high-speed processing and the high reliability are ambivalent at this system because of wireless communications between an IC card and an AFC gate; the faster the AFC gate processes the ticket, the poorer the reliability gets. In this thesis, it proposes the autonomous decentralized processing technology to meet high-speed processing in wireless IC ticket system and the requirement of high reliability. "IC card" "AFC" and "Central server" are assumed to be an autonomous system. It proposes "Decentralized algorithm of the fare calculation by IC card and the AFC" to achieve high-speed processing. Moreover, "Autonomous, decentralized consistency technology" in each subsystem is shown for high-reliability. In addition, to make these the effective one, "Wireless communication area enhancing technology (touch & going method)" and "Command system for the data high speed processing" are shown. These technologies are introduced into the Suica system of East Japan Railway and the effectiveness has been proven.

We propose a new end-to-end transport protocol called Multi-path Transmission Control Protocol (M/TCP) and its two robust acknowledgement (ACK) schemes. Our protocol is designed as an alternative TCP option to improve reliability and performance of the Internet. The M/TCP sender simultaneously transmits data via multiple controlled paths to the receiver. Our protocol requires no modification in IP layer. Two M/TCP endpoints establish multiple paths between them by subscribing to multiple ISPs. The two robust ACK schemes proposed in this paper aim at improving M/TCP performance over the Internet with high packet loss in ACK channels. Performances between our protocol and TCP Reno are compared in terms of throughput and fairness by using ns2 simulator. Simulation results indicate that M/TCP achieves higher throughput than TCP Reno in situation of random drop and burst traffic with small buffer size. When there is network congestion on reverse path, M/TCP with the proposed robust ACK schemes performs better than M/TCP with the conventional immediate ACK scheme.

When used for automotive applications, microcomputers have to meet two requirements more demanding than those for general use. One of these requirements is to respond to external events within a time scale of microseconds; the other is the high quality and high reliability necessary for the severe environmental operating conditions and the ambitious market requirements inherent to automotive applications. These needs especially the latter one have been responded to by further elaboration of each basic technology involved in semiconductor manufacturing. At the same time, various logic parts have been built into the microcomputer. This paper deals with several design approaches to the high quality and high reliability objective. First, testability improvement by the logical separation method focusing on the logic simulation model for generating test vectors, which enables us to reduce the time required for test vector development in half. Next, noise suppression methods to gain electromagnetic compatibility (EMC). Then, simplified memory transistor's analysis to evaluate the V/I-characteristics directly via external pins without opening the model seal, removing the passivation and placing a probe needle on the chip. Finally, increased reliability of on-chip EPROM using a special circuit raising the threshold value by approximately 1(V) compared to EPROM's without such a circuit.