Linear feedback shift register (LFSR) reseeding is an effective method for test data reduction. However, the test patterns generated by LFSR reseeding generally have high toggle rate and thus cause high test power. Therefore, it is feasible to fill X bits in deterministic test cubes with 0 or 1 properly before encoding the seed to reduce toggle rate. However, X-filling will increase the number of specified bits, thus increase the difficulty of seed encoding, what's more, the size of LFSR will increase as well. This paper presents a test frame which takes into consideration both compression ratio and power consumption simultaneously. In the first stage, the proposed reseeding-oriented X-filling proceeds for shift power (shift filling) and capture power (capture filling) reduction. Then, encode the filled test cubes using the proposed Compatible Block Code (CBC). The CBC can X-ize specified bits, namely turning specified bits into X bits, and can resolve the conflict between low-power filling and seed encoding. Experiments performed on ISCAS'89 benchmark circuits show that our scheme attains a compression ratio of 94.1% and reduces capture power by at least 15% and scan-in power by more than 79.5%.
Tian CHEN
Hefei University of Technology
Dandan SHEN
Hefei University of Technology
Xin YI
Hefei University of Technology
Huaguo LIANG
Hefei University of Technology
Xiaoqing WEN
Kyushu Institute of Technology
Wei WANG
Hefei University of Technology
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Tian CHEN, Dandan SHEN, Xin YI, Huaguo LIANG, Xiaoqing WEN, Wei WANG, "Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures" in IEICE TRANSACTIONS on Information,
vol. E99-D, no. 11, pp. 2672-2681, November 2016, doi: 10.1587/transinf.2015EDP7289.
Abstract: Linear feedback shift register (LFSR) reseeding is an effective method for test data reduction. However, the test patterns generated by LFSR reseeding generally have high toggle rate and thus cause high test power. Therefore, it is feasible to fill X bits in deterministic test cubes with 0 or 1 properly before encoding the seed to reduce toggle rate. However, X-filling will increase the number of specified bits, thus increase the difficulty of seed encoding, what's more, the size of LFSR will increase as well. This paper presents a test frame which takes into consideration both compression ratio and power consumption simultaneously. In the first stage, the proposed reseeding-oriented X-filling proceeds for shift power (shift filling) and capture power (capture filling) reduction. Then, encode the filled test cubes using the proposed Compatible Block Code (CBC). The CBC can X-ize specified bits, namely turning specified bits into X bits, and can resolve the conflict between low-power filling and seed encoding. Experiments performed on ISCAS'89 benchmark circuits show that our scheme attains a compression ratio of 94.1% and reduces capture power by at least 15% and scan-in power by more than 79.5%.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2015EDP7289/_p
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@ARTICLE{e99-d_11_2672,
author={Tian CHEN, Dandan SHEN, Xin YI, Huaguo LIANG, Xiaoqing WEN, Wei WANG, },
journal={IEICE TRANSACTIONS on Information},
title={Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures},
year={2016},
volume={E99-D},
number={11},
pages={2672-2681},
abstract={Linear feedback shift register (LFSR) reseeding is an effective method for test data reduction. However, the test patterns generated by LFSR reseeding generally have high toggle rate and thus cause high test power. Therefore, it is feasible to fill X bits in deterministic test cubes with 0 or 1 properly before encoding the seed to reduce toggle rate. However, X-filling will increase the number of specified bits, thus increase the difficulty of seed encoding, what's more, the size of LFSR will increase as well. This paper presents a test frame which takes into consideration both compression ratio and power consumption simultaneously. In the first stage, the proposed reseeding-oriented X-filling proceeds for shift power (shift filling) and capture power (capture filling) reduction. Then, encode the filled test cubes using the proposed Compatible Block Code (CBC). The CBC can X-ize specified bits, namely turning specified bits into X bits, and can resolve the conflict between low-power filling and seed encoding. Experiments performed on ISCAS'89 benchmark circuits show that our scheme attains a compression ratio of 94.1% and reduces capture power by at least 15% and scan-in power by more than 79.5%.},
keywords={},
doi={10.1587/transinf.2015EDP7289},
ISSN={1745-1361},
month={November},}
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TY - JOUR
TI - Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures
T2 - IEICE TRANSACTIONS on Information
SP - 2672
EP - 2681
AU - Tian CHEN
AU - Dandan SHEN
AU - Xin YI
AU - Huaguo LIANG
AU - Xiaoqing WEN
AU - Wei WANG
PY - 2016
DO - 10.1587/transinf.2015EDP7289
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E99-D
IS - 11
JA - IEICE TRANSACTIONS on Information
Y1 - November 2016
AB - Linear feedback shift register (LFSR) reseeding is an effective method for test data reduction. However, the test patterns generated by LFSR reseeding generally have high toggle rate and thus cause high test power. Therefore, it is feasible to fill X bits in deterministic test cubes with 0 or 1 properly before encoding the seed to reduce toggle rate. However, X-filling will increase the number of specified bits, thus increase the difficulty of seed encoding, what's more, the size of LFSR will increase as well. This paper presents a test frame which takes into consideration both compression ratio and power consumption simultaneously. In the first stage, the proposed reseeding-oriented X-filling proceeds for shift power (shift filling) and capture power (capture filling) reduction. Then, encode the filled test cubes using the proposed Compatible Block Code (CBC). The CBC can X-ize specified bits, namely turning specified bits into X bits, and can resolve the conflict between low-power filling and seed encoding. Experiments performed on ISCAS'89 benchmark circuits show that our scheme attains a compression ratio of 94.1% and reduces capture power by at least 15% and scan-in power by more than 79.5%.
ER -