The search functionality is under construction.

IEICE TRANSACTIONS on Information

A Low Capture Power Test Generation Method Based on Capture Safe Test Vector Manipulation

Toshinori HOSOKAWA, Atsushi HIRAI, Yukari YAMAUCHI, Masayuki ARAI

  • Full Text Views

    0

  • Cite this

Summary :

In at-speed scan testing, capture power is a serious problem because the high power dissipation that can occur when the response for a test vector is captured by flip-flops results in excessive voltage drops, known as IR-drops, which may cause significant capture-induced yield loss. In low capture power test generation, the test vectors that violate capture power constraints in an initial test set are defined as capture-unsafe test vectors, while faults that are detected solely by capture-unsafe test vectors are defined as unsafe faults. It is necessary to regenerate the test vectors used to detect unsafe faults in order to prevent unnecessary yield losses. In this paper, we propose a new low capture power test generation method based on fault simulation that uses capture-safe test vectors in an initial test set. Experimental results show that the use of this method reduces the number of unsafe faults by 94% while requiring just 18% more additional test vectors on average, and while requiring less test generation time compared with the conventional low capture power test generation method.

Publication
IEICE TRANSACTIONS on Information Vol.E100-D No.9 pp.2118-2125
Publication Date
2017/09/01
Publicized
2017/06/06
Online ISSN
1745-1361
DOI
10.1587/transinf.2016EDP7418
Type of Manuscript
PAPER
Category
Dependable Computing

Authors

Toshinori HOSOKAWA
  Nihon University
Atsushi HIRAI
  Nihon University
Yukari YAMAUCHI
  Nihon University
Masayuki ARAI
  Nihon University

Keyword