IEICE TRANSACTIONS on Information
DSP-Based Parallel Implementation of Speeded-Up Robust Features
Summary :
Robust local image features have become crucial components of many state-of-the-art computer vision algorithms. Due to limited hardware resources, computing local features on embedded system is not an easy task. In this paper, we propose an efficient parallel computing framework for speeded-up robust features with an orientation towards multi-DSP based embedded system. We optimize modules in SURF to better utilize the capability of DSP chips. We also design a compact data layout to adapt to the limited memory resource and to increase data access bandwidth. A data-driven barrier and workload balance schemes are presented to synchronize parallel working chips and reduce overall cost. The experiment shows our implementation achieves competitive time efficiency compared with related works.
- Publication
- IEICE TRANSACTIONS on Information Vol.E94-D No.4 pp.930-933
- Publication Date
- 2011/04/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E94.D.930
- Type of Manuscript
- LETTER
- Category
- Image Recognition, Computer Vision
Authors
Keyword
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Chao LIAO, Guijin WANG, Quan MIAO, Zhiguo WANG, Chenbo SHI, Xinggang LIN, "DSP-Based Parallel Implementation of Speeded-Up Robust Features" in IEICE TRANSACTIONS on Information,
vol. E94-D, no. 4, pp. 930-933, April 2011, doi: 10.1587/transinf.E94.D.930.
Abstract: Robust local image features have become crucial components of many state-of-the-art computer vision algorithms. Due to limited hardware resources, computing local features on embedded system is not an easy task. In this paper, we propose an efficient parallel computing framework for speeded-up robust features with an orientation towards multi-DSP based embedded system. We optimize modules in SURF to better utilize the capability of DSP chips. We also design a compact data layout to adapt to the limited memory resource and to increase data access bandwidth. A data-driven barrier and workload balance schemes are presented to synchronize parallel working chips and reduce overall cost. The experiment shows our implementation achieves competitive time efficiency compared with related works.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E94.D.930/_p
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@ARTICLE{e94-d_4_930,
author={Chao LIAO, Guijin WANG, Quan MIAO, Zhiguo WANG, Chenbo SHI, Xinggang LIN, },
journal={IEICE TRANSACTIONS on Information},
title={DSP-Based Parallel Implementation of Speeded-Up Robust Features},
year={2011},
volume={E94-D},
number={4},
pages={930-933},
abstract={Robust local image features have become crucial components of many state-of-the-art computer vision algorithms. Due to limited hardware resources, computing local features on embedded system is not an easy task. In this paper, we propose an efficient parallel computing framework for speeded-up robust features with an orientation towards multi-DSP based embedded system. We optimize modules in SURF to better utilize the capability of DSP chips. We also design a compact data layout to adapt to the limited memory resource and to increase data access bandwidth. A data-driven barrier and workload balance schemes are presented to synchronize parallel working chips and reduce overall cost. The experiment shows our implementation achieves competitive time efficiency compared with related works.},
keywords={},
doi={10.1587/transinf.E94.D.930},
ISSN={1745-1361},
month={April},}
Copy
TY - JOUR
TI - DSP-Based Parallel Implementation of Speeded-Up Robust Features
T2 - IEICE TRANSACTIONS on Information
SP - 930
EP - 933
AU - Chao LIAO
AU - Guijin WANG
AU - Quan MIAO
AU - Zhiguo WANG
AU - Chenbo SHI
AU - Xinggang LIN
PY - 2011
DO - 10.1587/transinf.E94.D.930
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E94-D
IS - 4
JA - IEICE TRANSACTIONS on Information
Y1 - April 2011
AB - Robust local image features have become crucial components of many state-of-the-art computer vision algorithms. Due to limited hardware resources, computing local features on embedded system is not an easy task. In this paper, we propose an efficient parallel computing framework for speeded-up robust features with an orientation towards multi-DSP based embedded system. We optimize modules in SURF to better utilize the capability of DSP chips. We also design a compact data layout to adapt to the limited memory resource and to increase data access bandwidth. A data-driven barrier and workload balance schemes are presented to synchronize parallel working chips and reduce overall cost. The experiment shows our implementation achieves competitive time efficiency compared with related works.
ER -
English
