Test Pattern Ordering and Selection for High Quality Test Set under Constraints

Michiko INOUE; Akira TAKETANI; Tomokazu YONEDA; Hideo FUJIWARA

doi:10.1587/transinf.E95.D.3001

Test Pattern Ordering and Selection for High Quality Test Set under Constraints

Michiko INOUE, Akira TAKETANI, Tomokazu YONEDA, Hideo FUJIWARA

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Nano-scale VLSI design is facing the problems of increased test data volume. Small delay defects are becoming possible sources of test escapes, and high delay test quality and therefore a greater volume of test data are required. The increased test data volume requires more tester memory and test application time, and both result in test cost inflation. Test pattern ordering gives a practical solution to reduce test cost, where test patterns are ordered so that more defects can be detected as early as possible. In this paper, we propose a test pattern ordering method based on SDQL (Statistical Delay Quality Level), which is a measure of delay test quality considering small delay defects. Our proposed method orders test patterns so that SDQL shrinks fast, which means more delay defects can be detected as early as possible. The proposed method efficiently orders test patterns with minimal usage of time-consuming timing-aware fault simulation. Experimental results demonstrate that our method can obtain test pattern ordering within a reasonable time, and also suggest how to prepare test sets suitable as inputs of test pattern ordering.

Publication: IEICE TRANSACTIONS on Information Vol.E95-D No.12 pp.3001-3009

Publication Date: 2012/12/01

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Online ISSN: 1745-1361

DOI: 10.1587/transinf.E95.D.3001

Type of Manuscript: PAPER

Category: Dependable Computing

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Michiko INOUE, Akira TAKETANI, Tomokazu YONEDA, Hideo FUJIWARA, "Test Pattern Ordering and Selection for High Quality Test Set under Constraints" in IEICE TRANSACTIONS on Information, vol. E95-D, no. 12, pp. 3001-3009, December 2012, doi: 10.1587/transinf.E95.D.3001.
Abstract: Nano-scale VLSI design is facing the problems of increased test data volume. Small delay defects are becoming possible sources of test escapes, and high delay test quality and therefore a greater volume of test data are required. The increased test data volume requires more tester memory and test application time, and both result in test cost inflation. Test pattern ordering gives a practical solution to reduce test cost, where test patterns are ordered so that more defects can be detected as early as possible. In this paper, we propose a test pattern ordering method based on SDQL (Statistical Delay Quality Level), which is a measure of delay test quality considering small delay defects. Our proposed method orders test patterns so that SDQL shrinks fast, which means more delay defects can be detected as early as possible. The proposed method efficiently orders test patterns with minimal usage of time-consuming timing-aware fault simulation. Experimental results demonstrate that our method can obtain test pattern ordering within a reasonable time, and also suggest how to prepare test sets suitable as inputs of test pattern ordering.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E95.D.3001/_p

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@ARTICLE{e95-d_12_3001,
author={Michiko INOUE, Akira TAKETANI, Tomokazu YONEDA, Hideo FUJIWARA, },
journal={IEICE TRANSACTIONS on Information},
title={Test Pattern Ordering and Selection for High Quality Test Set under Constraints},
year={2012},
volume={E95-D},
number={12},
pages={3001-3009},
abstract={Nano-scale VLSI design is facing the problems of increased test data volume. Small delay defects are becoming possible sources of test escapes, and high delay test quality and therefore a greater volume of test data are required. The increased test data volume requires more tester memory and test application time, and both result in test cost inflation. Test pattern ordering gives a practical solution to reduce test cost, where test patterns are ordered so that more defects can be detected as early as possible. In this paper, we propose a test pattern ordering method based on SDQL (Statistical Delay Quality Level), which is a measure of delay test quality considering small delay defects. Our proposed method orders test patterns so that SDQL shrinks fast, which means more delay defects can be detected as early as possible. The proposed method efficiently orders test patterns with minimal usage of time-consuming timing-aware fault simulation. Experimental results demonstrate that our method can obtain test pattern ordering within a reasonable time, and also suggest how to prepare test sets suitable as inputs of test pattern ordering.},
keywords={},
doi={10.1587/transinf.E95.D.3001},
ISSN={1745-1361},
month={December},}

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TY - JOUR
TI - Test Pattern Ordering and Selection for High Quality Test Set under Constraints
T2 - IEICE TRANSACTIONS on Information
SP - 3001
EP - 3009
AU - Michiko INOUE
AU - Akira TAKETANI
AU - Tomokazu YONEDA
AU - Hideo FUJIWARA
PY - 2012
DO - 10.1587/transinf.E95.D.3001
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E95-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2012
AB - Nano-scale VLSI design is facing the problems of increased test data volume. Small delay defects are becoming possible sources of test escapes, and high delay test quality and therefore a greater volume of test data are required. The increased test data volume requires more tester memory and test application time, and both result in test cost inflation. Test pattern ordering gives a practical solution to reduce test cost, where test patterns are ordered so that more defects can be detected as early as possible. In this paper, we propose a test pattern ordering method based on SDQL (Statistical Delay Quality Level), which is a measure of delay test quality considering small delay defects. Our proposed method orders test patterns so that SDQL shrinks fast, which means more delay defects can be detected as early as possible. The proposed method efficiently orders test patterns with minimal usage of time-consuming timing-aware fault simulation. Experimental results demonstrate that our method can obtain test pattern ordering within a reasonable time, and also suggest how to prepare test sets suitable as inputs of test pattern ordering.
ER -