A Modularized <I>b</I>-Adjacent Error Correction Memory Unit

Eiji FUJIWARA

A Modularized b-Adjacent Error Correction Memory Unit

Eiji FUJIWARA

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This paper demonstrates that the practical implementation of single b-Adjacent bit-group Error Correcting (SbEC) Code gives a modularized high reliability memory unit. By the application of rotational coding techniques to this code, not only a high speed parallel encoding/decoding network (memory translator), but also a memory unit can be organized in modular distributed forms, well suited for applying the LSI logic technologies to this memory translator and for achieving the high reliability and high maintainability memory unit. The parity check matrix of this code, which is easily decodable, can be expressed by the rotational operating matrix and the basic generating-submatrix. The basic hardware implementation of each modular organized translator consists of three circuitry portions which can be well designed for LSI logic. As an illustrative example, the most practical and optimum rotational (72, 64) S2EC code is implemented. The translator of this code is organized in four modular distributed forms. LSI logic patterns of each translator module require 30 to 50 input-output leads and 100 to 270 gates. The operational speed of this translator is almost equal to that of the conventional high speed SEC-DED (Single Error Correcting - Double Error Detecting) codes. As a result, this memory unit consists of four identical modules, each of which includes not only one of these translator modules, but also a storage portion and a input-output selector portion.

Publication: IEICE TRANSACTIONS on transactions Vol.E60-E No.2 pp.69-76

Publication Date: 1977/02/25

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Type of Manuscript: PAPER

Category: Computers

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Eiji FUJIWARA

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Eiji FUJIWARA, "A Modularized b-Adjacent Error Correction Memory Unit" in IEICE TRANSACTIONS on transactions, vol. E60-E, no. 2, pp. 69-76, February 1977, doi: .
Abstract: This paper demonstrates that the practical implementation of single b-Adjacent bit-group Error Correcting (SbEC) Code gives a modularized high reliability memory unit. By the application of rotational coding techniques to this code, not only a high speed parallel encoding/decoding network (memory translator), but also a memory unit can be organized in modular distributed forms, well suited for applying the LSI logic technologies to this memory translator and for achieving the high reliability and high maintainability memory unit. The parity check matrix of this code, which is easily decodable, can be expressed by the rotational operating matrix and the basic generating-submatrix. The basic hardware implementation of each modular organized translator consists of three circuitry portions which can be well designed for LSI logic. As an illustrative example, the most practical and optimum rotational (72, 64) S2EC code is implemented. The translator of this code is organized in four modular distributed forms. LSI logic patterns of each translator module require 30 to 50 input-output leads and 100 to 270 gates. The operational speed of this translator is almost equal to that of the conventional high speed SEC-DED (Single Error Correcting - Double Error Detecting) codes. As a result, this memory unit consists of four identical modules, each of which includes not only one of these translator modules, but also a storage portion and a input-output selector portion.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e60-e_2_69/_p

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@ARTICLE{e60-e_2_69,
author={Eiji FUJIWARA, },
journal={IEICE TRANSACTIONS on transactions},
title={A Modularized b-Adjacent Error Correction Memory Unit},
year={1977},
volume={E60-E},
number={2},
pages={69-76},
abstract={This paper demonstrates that the practical implementation of single b-Adjacent bit-group Error Correcting (SbEC) Code gives a modularized high reliability memory unit. By the application of rotational coding techniques to this code, not only a high speed parallel encoding/decoding network (memory translator), but also a memory unit can be organized in modular distributed forms, well suited for applying the LSI logic technologies to this memory translator and for achieving the high reliability and high maintainability memory unit. The parity check matrix of this code, which is easily decodable, can be expressed by the rotational operating matrix and the basic generating-submatrix. The basic hardware implementation of each modular organized translator consists of three circuitry portions which can be well designed for LSI logic. As an illustrative example, the most practical and optimum rotational (72, 64) S2EC code is implemented. The translator of this code is organized in four modular distributed forms. LSI logic patterns of each translator module require 30 to 50 input-output leads and 100 to 270 gates. The operational speed of this translator is almost equal to that of the conventional high speed SEC-DED (Single Error Correcting - Double Error Detecting) codes. As a result, this memory unit consists of four identical modules, each of which includes not only one of these translator modules, but also a storage portion and a input-output selector portion.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - A Modularized b-Adjacent Error Correction Memory Unit
T2 - IEICE TRANSACTIONS on transactions
SP - 69
EP - 76
AU - Eiji FUJIWARA
PY - 1977
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E60-E
IS - 2
JA - IEICE TRANSACTIONS on transactions
Y1 - February 1977
AB - This paper demonstrates that the practical implementation of single b-Adjacent bit-group Error Correcting (SbEC) Code gives a modularized high reliability memory unit. By the application of rotational coding techniques to this code, not only a high speed parallel encoding/decoding network (memory translator), but also a memory unit can be organized in modular distributed forms, well suited for applying the LSI logic technologies to this memory translator and for achieving the high reliability and high maintainability memory unit. The parity check matrix of this code, which is easily decodable, can be expressed by the rotational operating matrix and the basic generating-submatrix. The basic hardware implementation of each modular organized translator consists of three circuitry portions which can be well designed for LSI logic. As an illustrative example, the most practical and optimum rotational (72, 64) S2EC code is implemented. The translator of this code is organized in four modular distributed forms. LSI logic patterns of each translator module require 30 to 50 input-output leads and 100 to 270 gates. The operational speed of this translator is almost equal to that of the conventional high speed SEC-DED (Single Error Correcting - Double Error Detecting) codes. As a result, this memory unit consists of four identical modules, each of which includes not only one of these translator modules, but also a storage portion and a input-output selector portion.
ER -