This paper demonstrates that the practical implementation of single b-Adjacent bit-group Error Correcting (SbEC) Code gives a modularized high reliability memory unit. By the application of rotational coding techniques to this code, not only a high speed parallel encoding/decoding network (memory translator), but also a memory unit can be organized in modular distributed forms, well suited for applying the LSI logic technologies to this memory translator and for achieving the high reliability and high maintainability memory unit. The parity check matrix of this code, which is easily decodable, can be expressed by the rotational operating matrix and the basic generating-submatrix. The basic hardware implementation of each modular organized translator consists of three circuitry portions which can be well designed for LSI logic. As an illustrative example, the most practical and optimum rotational (72, 64) S2EC code is implemented. The translator of this code is organized in four modular distributed forms. LSI logic patterns of each translator module require 30 to 50 input-output leads and 100 to 270 gates. The operational speed of this translator is almost equal to that of the conventional high speed SEC-DED (Single Error Correcting - Double Error Detecting) codes. As a result, this memory unit consists of four identical modules, each of which includes not only one of these translator modules, but also a storage portion and a input-output selector portion.

Given a set of n data records with L_i, data length and P_i, access frequency of data record R_i (1in), each data record is allocated in one of buckets, whose size is L, minimizing the access delay D,
DP_i・P_j・d_ij
d_ij: distance from allocated data record R_i to R_j, while satisfying the constraint that the size of data records in each bucket does not exceed L. The property of optimal allocation is investigated and an allocation heuristic is given whose slight modification gives the optimal allocation for the data records of up to 2 unit data length.