IEICE TRANSACTIONS on transactions
The Architecture of a Flexible Servo Motor Control Processor--FSP-3--
Summary :
This letter describes the architecture and ASIC implementation of the FSP-3 (Flexible Servo motor control Processor-3) chip. The FSP-3 is a special purpose 32 bit microprocessor dedicated to the Flexible Servo Control System (FSC), which is able to manipulate various kinds of servo motors efficiently. FSP-3 chip is one of the largest scale system ASICs entirely designed in Japanese universities.
- Publication
- IEICE TRANSACTIONS on transactions Vol.E73-E No.4 pp.513-515
- Publication Date
- 1990/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section LETTER (Special Issue on 1990 Spring National Convention IEICE)
- Category
- Integrated Circuits
Authors
Jun SATO
Tsutomu KIMURA
Masaharu IMAI
Frank de SCHEPPER
Kazuo YAMAZAKI
Masashi NAGASE
Shin-ichiro YAMAMOTO
Keyword
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Jun SATO, Tsutomu KIMURA, Masaharu IMAI, Frank de SCHEPPER, Kazuo YAMAZAKI, Masashi NAGASE, Shin-ichiro YAMAMOTO, "The Architecture of a Flexible Servo Motor Control Processor--FSP-3--" in IEICE TRANSACTIONS on transactions,
vol. E73-E, no. 4, pp. 513-515, April 1990, doi: .
Abstract: This letter describes the architecture and ASIC implementation of the FSP-3 (Flexible Servo motor control Processor-3) chip. The FSP-3 is a special purpose 32 bit microprocessor dedicated to the Flexible Servo Control System (FSC), which is able to manipulate various kinds of servo motors efficiently. FSP-3 chip is one of the largest scale system ASICs entirely designed in Japanese universities.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e73-e_4_513/_p
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@ARTICLE{e73-e_4_513,
author={Jun SATO, Tsutomu KIMURA, Masaharu IMAI, Frank de SCHEPPER, Kazuo YAMAZAKI, Masashi NAGASE, Shin-ichiro YAMAMOTO, },
journal={IEICE TRANSACTIONS on transactions},
title={The Architecture of a Flexible Servo Motor Control Processor--FSP-3--},
year={1990},
volume={E73-E},
number={4},
pages={513-515},
abstract={This letter describes the architecture and ASIC implementation of the FSP-3 (Flexible Servo motor control Processor-3) chip. The FSP-3 is a special purpose 32 bit microprocessor dedicated to the Flexible Servo Control System (FSC), which is able to manipulate various kinds of servo motors efficiently. FSP-3 chip is one of the largest scale system ASICs entirely designed in Japanese universities.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - The Architecture of a Flexible Servo Motor Control Processor--FSP-3--
T2 - IEICE TRANSACTIONS on transactions
SP - 513
EP - 515
AU - Jun SATO
AU - Tsutomu KIMURA
AU - Masaharu IMAI
AU - Frank de SCHEPPER
AU - Kazuo YAMAZAKI
AU - Masashi NAGASE
AU - Shin-ichiro YAMAMOTO
PY - 1990
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E73-E
IS - 4
JA - IEICE TRANSACTIONS on transactions
Y1 - April 1990
AB - This letter describes the architecture and ASIC implementation of the FSP-3 (Flexible Servo motor control Processor-3) chip. The FSP-3 is a special purpose 32 bit microprocessor dedicated to the Flexible Servo Control System (FSC), which is able to manipulate various kinds of servo motors efficiently. FSP-3 chip is one of the largest scale system ASICs entirely designed in Japanese universities.
ER -
English
