This paper presents a step-up/step-down DC-DC converter with three operation modes to achieve high efficiency and small output ripple voltage. A constant time buck-boost mode, which is inserted between buck mode and boost mode, is proposed to achieve smooth transition. With the proposed mode, the output ripple voltage is significantly reduced when the input voltage is approximate to the output voltage. Besides, the novel control scheme minimizes the conduction loss by reducing the average inductor current and the switching loss by making the converter operate like a buck or boost converter. The small signal model of the step-up/step-down DC-DC converter is also derived to guide the compensation network design. The step-up/step-down converter is designed with a 0.5 µm CMOS n-well process, and can regulate an output voltage within the input voltage ranged from 2.5 V to 5.5 V with a maximum power efficiency of 96%. The simulation results show that the proposed converter exhibits an output ripple voltage of 28 mV in the transition mode.

Multi-hypothesis prediction technique, which exploits inter-frame correlation efficiently, is widely used in block-based distributed compressive video sensing. To solve the problem of inaccurate prediction in multi-hypothesis prediction technique at a low sampling rate and enhance the reconstruction quality of non-key frames, we present a resample-based hybrid multi-hypothesis scheme for block-based distributed compressive video sensing. The innovations in this paper include: (1) multi-hypothesis reconstruction based on measurements reorganization (MR-MH) which integrates side information into the original measurements; (2) hybrid multi-hypothesis (H-MH) reconstruction which mixes multiple multi-hypothesis reconstructions adaptively by resampling each reconstruction. Experimental results show that the proposed scheme outperforms the state-of-the-art technique at the same low sampling rate.

This paper presents a step-up/step-down DC-DC converter using a digital dither technique to achieve high efficiency and small output voltage ripple for portable electronic devices. The proposed control method minimizes not only the switching loss by operating like a pure buck or boost converter, but also the conduction loss by reducing the average inductor current even when four switches are used. Digital dither control is introduced to implement a buffer region for smooth transition between buck and boost modes. A minimum ripple dither with higher fundamental frequency is adopted to decrease the output voltage ripple. A window delay-line analog to digital converter (ADC) with delay calibration is achieved to digitalize the control voltage. The step-up/step-down DC-DC converter has been designed with a standard 0.5 µm CMOS process. The output voltage is regulated within the input voltage ranged from 2.5 V to 5.5 V, and the output voltage ripple is reduced to less than 25 mV during the mode transition. The peak power efficiency is 96%, and the maximum load current can reach 800 mA.

Common schedulers for long-term running services that perform task-level optimization fail to accommodate short-living batch processing (BP) jobs. Thus, many efficient job-level scheduling strategies are proposed for BP jobs. However, the existing scheduling strategies perform time-consuming objective optimization which yields non-negligible scheduling delay. Moreover, they tend to assign BP jobs in a centralized manner to reduce monetary cost and synchronization overhead, which can easily cause resource contention due to the task co-location. To address these problems, this paper proposes TEBAS, a time-efficient balance-aware scheduling strategy, which spreads all tasks of a BP job into the cluster according to the resource specifications of a single task based on the observation that computing tasks of a BP job commonly possess similar features. The experimental results show the effectiveness of TEBAS in terms of scheduling efficiency and load balancing performance.

Time-interleaving is an efficient approach to increase the effective sampling rate of the ΣΔ modulators, but time-interleaved (TI) ΣΔ modulators are sensitive to channel mismatch, which causes the quantization noise folded back into the band of interest. To reduce the folded noise caused by the channel mismatch of two-channel TI ΣΔ modulators, a low-power second-order two-channel TI ΣΔ modulator is proposed. The noise transfer function (NTF) of the modulator is a band-pass filter. By using this band-pass NTF, the folded noised can be reduced. The entire modulator can be implemented by employing three op-amps, which is beneficial for power consumption. The circuit of implementation for the proposed modulator is designed in 0.18 µm COMS technology. The proposed modulator can achieve a SNDR of 78.9 dB with a channel mismatch of 0.5% and a linear gradient mismatch of 0.4% for unity sampling capacitors. Monte Carlo simulation is done with a random Gaussian mismatch of 0.4% standard deviation for all capacitors, resulting in an average SNDR of 80.5 dB. It is indicated that the proposed TI modulator is insensitive to the channel mismatch. The total power consumption is 19.5 mW from a 1.8 V supply.

Distributed compressive video sensing (DCVS) has received considerable attention due to its potential in source-limited communication, e.g., wireless video sensor networks (WVSNs). Multi-hypothesis (MH) prediction, which treats the target block as a linear combination of hypotheses, is a state-of-the-art technique in DCVS. The common approach is under the supposition that blocks that are dissimilar from the target block are given lower weights than blocks that are more similar. This assumption can yield acceptable reconstruction quality, but it is not suitable for scenarios with more details. In this paper, based on the joint sparsity model (JSM), the authors present a Tikhonov-regularized MH prediction scheme in which the most similar block provides the similar common portion and the others blocks provide respective unique portions, differing from the common supposition. Specifically, a new scheme for generating hypotheses and a Euclidean distance-based metric for the regularized term are proposed. Compared with several state-of-the-art algorithms, the authors show the effectiveness of the proposed scheme when there are a limited number of hypotheses.

This paper presents a systemic analysis for phase noise performances of differential cross-coupled LC oscillators by using Hajimiri and Lee's model. The effective impulse sensitivity functions (ISF) for each noise source in the oscillator is mathematically derived. According to these effective ISFs, the phase noise contribution from each device is figured out, and phase noise contributions from the device noise in the vicinity of the integer multiples of the resonant frequency, weighted by the Fourier coefficients of the effective ISF, are also calculated. The explicit closed-form expression for phase noise of the oscillator is definitely determined. The validity of the phase noise analysis is verified by good simulation agreement.

This paper presents a systemic analysis for phase noise performances of the series quadrature oscillator (QOSC) by using the time-variant impulse sensitivity function (ISF) model. The effective ISF for each noise source in the oscillator is derived mathematically. According to these effective ISFs, the explicit closed-form expression for phase noise due to the total thermal noise in the series QOSC is derived, and the phase noise contribution from the flicker noise in the regenerative and coupling transistors is also figured out. The phase noise contributions from the thermal noise and the flicker noise are verified by SpectreRF simulations.