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[Author] Kyung PARK(7hit)

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  • On the Sum-Rate Capacity of Multi-User Distributed Antenna System with Circular Antenna Layout

    Jiansong GAN  Shidong ZHOU  Jing WANG  Kyung PARK  

     
    LETTER-Fundamental Theories for Communications

      Vol:
    E89-B No:9
      Page(s):
    2612-2616

    In this letter, we investigate the sum-rate capacity of a power-controlled multi-user distributed antenna system (DAS) with antennas deployed symmetrically on a circle. The sum-rate capacity, when divided by user number, is proved to converge to an explicit expression as user number and antenna number go to infinity with a constant ratio. We further show how this theoretical result can be used to optimize antenna deployment. Simulation results are also provided to demonstrate the validity of our analysis and the applicability of the asymptotic results to a small-scale system.

  • Outage Probability Based Optimal Transmission of Space Time Block Codes over Correlated Distributed Antennas

    Shuangfeng HAN  Shidong ZHOU  Ming ZHAO  Jing WANG  Kyung PARK  

     
    PAPER-Wireless Communication Technologies

      Vol:
    E89-B No:9
      Page(s):
    2514-2521

    Aiming to optimally transmit space-time block codes (STBCs) over distributed antennas (DAs), this paper examines downlink transmit antenna subset selection with power allocation for STBCs in non-ergodic Rayleigh fading channels with receive antenna correlations. Closed-form outage probability is first derived, which is a function of data rate, rate of STBCs, transmit power, large-scale fading (shadowing and path loss), power allocation weights to each DA and receive antenna correlation. However, achieving the optimal power allocation solution is computationally demanding and the use of sub-optimal techniques is necessitated. Assuming feedback of eigenvalues of transmit and receive antenna correlation matrix at the transmitter and accurate channel state information (CSI) at the receiver, an antenna subset selection with sub-optimal power allocation scheme is proposed, whose performance approaches optimal. The effectiveness of this sub-optimal method has been demonstrated by numerical results.

  • Energy-Aware Pure ALOHA for Wireless Sensor Networks

    Jin Kyung PARK  Woo Cheol SHIN  Jun HA  Cheon Won CHOI  

     
    PAPER

      Vol:
    E89-A No:6
      Page(s):
    1638-1646

    A wireless sensor network is a network of compact micro-sensors equipped with wireless communication capability. In a wireless sensor network, saving energy is a critical issue. Furthermore, a sensor node is expected to face many difficulties in signaling and computing. As a MAC scheme for a wireless sensor network, we thus propose an energy-aware version of pure ALOHA scheme, where rather than sacrificing the simplicity of pure ALOHA, we take a straightforward approach in saving energy by trading off throughput performance. First, we add a step of deciding between stop and continuation prior to each delivery attempt for a MAC PDU. Secondly, we find an optimal stopping rule for such a decision in consideration of the losses reflecting energy consumption as well as throughput degradation. In particular, we note that the results of delivery attempts are hardly predictable in the environment that sensor nodes contend for the error-prone wireless resource. Thus, presuming that only partial information about such results is available to sensor nodes, we explicitly draw an optimal stopping rule. Finally, numerical examples are given to demonstrate the expected losses incurred by optimal stopping rules with full and partial information.

  • A Low-Jitter Delay-Locked Loop with Harmonic-Lock Prevention

    Sungkyung PARK  Changsik YOO  Sin-Chong PARK  

     
    LETTER-Circuit Theory

      Vol:
    E85-A No:2
      Page(s):
    505-507

    A multiphase low-jitter delay-locked loop (DLL) with harmonic-lock prevention, targeted at a gigabit parallel link interface, is delineated. A three-input four-state dynamic phase detector (PD) is proposed to obviate harmonic locking. Employing a low-jitter delay element and a new type of PD, the DLL is compact and feasible in its nature. The DLL is designed using a 0.35 µm 2P4M CMOS process with 3.3 V supply. Experimental results show that the circuit avoids false locking.

  • A Fractional-N PLL with Dual-Mode Detector and Counter

    Fitzgerald Sungkyung PARK  Nikolaus KLEMMER  

     
    BRIEF PAPER-Integrated Electronics

      Vol:
    E95-C No:12
      Page(s):
    1887-1890

    A fractional-N phase-locked loop (PLL) is designed for the DigRF interface. The digital part of the PLL mainly consists of a dual-mode phase frequency detector (PFD), a digital counter, and a digital delta-sigma modulator (DSM). The PFD can operate on either 52 MHz or 26 MHz reference frequencies, depending on its use of only the rising edge or both the rising and the falling edges of the reference clock. The interface between the counter and the DSM is designed to give enough timing margin in terms of the signal round-trip delay. The circuitry is implemented using a 90-nm CMOS process technology with a 1.2-V supply, draining 1 mA.

  • Conservative Extension of Connection Retrieval Time for Wireless Packet Service

    Cheon Won CHOI  Woo Cheol SHIN  Jin Kyung PARK  Jun HA  Ho-Kyoung LEE  

     
    PAPER

      Vol:
    E87-A No:6
      Page(s):
    1417-1425

    In provisioning packet data service on wireless cellular networks, a scheme of altering connection status between mobile and base stations appeared intending to efficiently utilize resource during idle periods. In such a scheme, connection components are sequentially released as an idle period persists, while the transmitting station converts to an transmission activity mode as the station is loaded with packets. However, actual resume of transmission activity is postponed by connection retrieval time to restore lost connection components. In general, an idle period affects the following connection retrieval time, which in turn produces an impact on the forthcoming idle period. Such chain reaction also makes a significant influence on overall packet delay performance. In this paper, as a way of improving packet delay performance, we propose two schemes identified as conservative extension and load threshold schemes. In the conservative extension scheme, we intentionally extend connection retrieval times so that each connection retrieval time is guaranteed not to be lower than a certain value. On the other hand, according to the load threshold scheme, a retrieval of lost connection components is postponed until packets are accumulated at the transmitting station up to a prescribed threshold. An increase in the value and threshold incurs an additional stand-by before resuming transmission activity in both proposed schemes. In turn, such intentional stand-by may contribute to regulating the length of idle period and connection retrieval time, and subsequently improving packet delay performance. To inspect the impact of conservative extension and load threshold schemes on packet delay performance, we first investigate the properties of idle periods. Secondly, for Poisson packet arrivals, we present an analytical method to exactly calculate the moments of packet delay time (at steady state) in each scheme. From numerical examples, we confirm the existence of non-trivial optimal value and threshold minimizing average packet delay or packet delay variation and conclude that conservative extension and load threshold schemes are able to enhance packet delay performance in various environments.

  • Digital Compensation of IQ Imbalance for Dual-Carrier Double Conversion Receivers

    Chester Sungchung PARK  Fitzgerald Sungkyung PARK  

     
    PAPER-Transmission Systems and Transmission Equipment for Communications

      Vol:
    E95-B No:5
      Page(s):
    1612-1619

    A receiver architecture and a digital IQ imbalance compensation method for dual-carrier reception are newly proposed. The impact of IQ imbalance on the baseband signal is mathematically analyzed. Based on the analysis, IQ imbalance parameters are estimated and the coupling effect of IQ imbalance is compensated using digital baseband processing alone. Simulation results show that the proposed IQ imbalance compensation successfully removes IQ imbalance. The deviation from the ideal performance is less than 1 dB when it is applied to the 3GPP-LTE carrier aggregation.