The structure of the nanograting channel MOSFET was optimized by simply rounding the corners of the nanogratings. The current drivabilities of the optimized nanograting channel MOSFETs were enhanced by about 20% and 50% for both n-channel and p-channel MOSFETs, respectively. The mobility changes were analyzed on the basis of channel stress as well as theoretical change of mobilities by various surface orientations. The internal compressive stress of 0.23% was measured in the channel. By suppressing the electric field increase at the corner edge of the nanograting channel to less than 10%, the fabricated rounded nanograting MOSFETs achieved lifetimes of NBTI and TDDB as long as those of conventional planar devices.

A convolutional neural network (CNN) for broadband direction of arrival (DOA) estimation of far-field electromagnetic signals is presented. The proposed algorithm performs a nonlinear inverse mapping from received signal to angle of arrival. The signal model used for algorithm is based on the circular antenna array geometry, and the phase component extracted from the spatial covariance matrix is used as the input of the CNN network. A CNN model including three convolutional layers is then established to approximate the nonlinear mapping. The performance of the CNN model is evaluated in a noisy environment for various values of signal-to-noise ratio (SNR). The results demonstrate that the proposed CNN model with the phase component of the spatial covariance matrix as the input is able to achieve fast and accurate broadband DOA estimation and attains perfect performance at lower SNR values.

Drivability-improved MOSFETs were successfully fabricated by using nano-grating silicon wafers. There was almost no additional process change in device fabrication when the height of the gratings was less than the conventional macroscopic wafer surface roughness. The MOSFETs with the grating height of 35 nm showed 21% improvement in current drivability compared to the conventional one with the same device occupancy area. And the roll-off characteristic of threshold voltage of nano-grating device held the line of conventional one in despite of the 3-D channel structure. The technology provides great advantages for drivability improvement without paying much tradeoff of process cost. This proposal will be useful to CMOS-LSIs with high performance in general.

Recently, due to the development of design and manufacturing technologies for VLSI systems, an embedded system becomes more and more complex. Consequently, not only the performance of chips, but also the flexibility and dynamic adaptation of the implemented systems are required. To achieve these requirements, a partially reconfigurable device is promising. In this paper, we propose an efficient data structure to manage the reconfigurable units. And then, on the assumption that each task utilizes the rectangle shaped resources, a very simple MER enumeration algorithm based on this data structure is proposed. By utilizing the result of MER enumeration, the free space on the reconfigurable device can be used sufficiently. We analyze the complexity of the proposed algorithm and confirm its efficiency by experiments.