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Shingo MANDAI Taihei MOMMA Makoto IKEDA Kunihiro ASADA
This paper presents an architecture and a circuit design of readout address compression for a high-speed 3-D range-finding image sensor using the light-section method. We utilize a kind of variable-length code which is modified to suit the 3-D range-finder. The best compression rate by the proposed compression technique is 33.3%. The worst compression and the average compression rate is 56.4% and 42.4%, respectively, when we simulated the effectivity by using the example of measured sheet scans. We also show the measurement result of the fabricated image sensor with the address compression.
Toru NAKURA Shingo MANDAI Makoto IKEDA Kunihiro ASADA
This paper presents a Time Difference Amplifier (TDA) that amplifies the input time difference into the output time difference. Cross coupled chains of variable delay cells with the same number of stages are applicable for TDA, and the gain is adjusted via the closed-loop control. The TDA was fabricated using 65 nm CMOS and the measurement results show that the time difference gain is 4.78 at a nominal power supply while the designed gain is 4.0. The gain is stable enough to be less than 1.4% gain shift under 10% power supply voltage fluctuation.
Shingo MANDAI Toru NAKURA Makoto IKEDA Kunihiro ASADA
This paper presents a multi functional range finder employing dual imager core on a single chip. Each imager core has functionalities of 2-D imaging and 3-D capture using the light section method with combinations of the dual imager core. The presented chip achieves, 2-D imaging mode, 3-D capture mode with the conventional light-section method, high-speed 3-D capture mode with the stereo matching mode, and 2-D and 3-D simultaneous capture mode. We demonstrate 58 fps 2-D imaging with 8 bit gray scale, and 24.8 rangemaps/s 3-D range-finder with the maximum range error of 1.619 mm and the standard deviation of 0.385 mm at 700 mm.
Shingo MANDAI Toru NAKURA Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA
We introduce a 16 × cascaded time difference amplifier (TDA) using a differential logic delay cell with 0.18 µm CMOS process. By employing the differential logic delay cell in the delay chain instead of the CMOS logic delay cell, less than 8% TD gain offset with 150 ps input range is achieved. The input referred standard deviation of the output time difference error is 2.7 ps and the input referred is improved by 17% compared with that of the previous TDA using the CMOS logic delay cell.
Shingo MANDAI Tetsuya IIZUKA Toru NAKURA Makoto IKEDA Kunihiro ASADA
This paper proposes a time-to-digital converter (TDC) utilizing the cascaded time difference amplifier (TDA) and shows measurement results with 0.18 µm CMOS. The proposed TDC operates in two modes, a wide input range mode and a fine time resolution mode. We employ a non-linearity calibration technique based on a lookup table. The wide input range mode shows 10.2 ps time resolution over 1.3 ns input range with DNL and INL of +0.8/-0.7LSB and +0.8/-0.4LSB, respectively. The fine time resolution mode shows 1.0 ps time resolution over 60 ps input range with DNL and INL of +0.9/-0.9LSB and +0.8/-1.0LSB, respectively.