This paper describes a reduction algorithm for SW method which generates test sequences for communication systems. SW method is based upon the Finite State Machine (FSM). SW method uses a set of characterizing sequences and a state transition checking approach. This paper concentrates the characteristics of the SW sequences, and proposes the new derivation algorithm of characterizing sequences. Furthermore, Chinese Postman Tour and Extended Chinese Postman Tour is proposed to reduce redundancy of the SW sequences. This paper also presents an evaluation of this method in terms of an upper bound of the sequence length and generated test sequence length. The evaluation shows that the algorithm dramatically reduces the sequence length of the original method.

This paper surveys modeling techniques for telephone call control based on a Finite State Machine (FSM) concept, and studies model simplification techniques. First, the basic concept and fundamental issues of call control modeling are described. Then, based on the analysis of layered call control configuration, it is clarified that the call control machine decomposition within the two-party service control layer has the effect of reducing the apparent size of each mate's machine. Using this effect, guidelines for call control modeling are derived, by which multiple services can be modeled independently. Finally implementation techniques and a few examples of application will be presented.

Many practical communication protocols provide priority service as well as ordinary service. In such a protocol, the protocol machines can initiate a priority service at most of the states. This characteristic leads an extreme increment of the number of state transitions on the protocol machines and causes state space explosion in verification of safety property of the protocol. This paper describes a method of constructing a communication protocol from composition of a subprotocol for ordinary service and that for priority service. This paper also presents a sufficient condition for a composed protocol to inherit safety property from the subprotocols. By using the composition method and the sufficient condition, the decision problem for safety property of the composed protocol can be reduced to those of the subprotocols. An experimental result of verification of a part of OSI session protocol is also described. The result shows that the method can reduce the computation time for verifying safety property to about 3% against the naive way.

This paper presents a protocol verification method which verifies that the behaviors of a protocol meet requirements. In this method, a protocol specification is expressed as Extended Finite State Machines (EFSM's) that can handle variables, and requirements are expressed using a branching-time temporal logic for a concise and unambiguous description. Using the acyclic expansion algorithm extended such that it can deal with EFSM's, the verification method first generates a state transition graph consisting of executable transitions for each process. Then a branching-time temporal logic formula representing a requirement is evaluated on one of the generated graphs which is relevant to the requirement. An executable state transition graph for each process is much smaller than a global state transition graph which has been used in the conventional verification techniques to represent the behaviors of the whole protocol system consisting of all processes. The computation for generating the graphs is also reduced to much extent for a large complex protocol. As a result, the presented method achieves efficient verification for requirements regarding a state of a process, transmission and reception of messages by a process, varibales of a process and sequences that interact among processes. The validity of the method is illustrated in the paper by the verification of a path-updating protocol for requirements such as process state reachability or fair termination among processes.

Recently, Burch et al. proposed symbolic model checking method to verify sequential machines formally. The method, which is based on logic function manipulation using binary decision diagram, can handle large sequential machines that cannot be handled by the conventional techniques. The expressive power of Computational Tree Logic (CTL), which was used by Burch et al., is not very powerful, for example, CTL cannot describe repetition of events. This papers shows an extension of the symbolic model checking algorithm to Branching time regular temporal logic (BRTL), which has been proposed by the authors as an improvement of CTL in terms of expressive power. The implemented verifier based on the proposed algorithm could verify behaviors of a microprocessor composed of approximately 1,600 gates and 68 flipflops.

This paper proposes a test case generation method for testing concurrent programs as a black box. Typical applications are system testing for switching systems and inter-operability testing for OSI products. We adopt a two-step approach: first generate the control flow graph which represents global behaviors of a given concurrent program, and then apply conventional test case generation methods for the control flow graph. To generate a control flow graph without state space explosion, the black-box equivalence between system behaviors is introduced. The proposed algorithm generates a minimal control flow graph which consists of representatives of equivalence classes. Two practical techniques for the second step are discussed for a case study using a commercial digital PBX. The results show the feasibility of the proposed method.

This paper deals with the problem of translating Japanese adnominal particles into English according to the idea of Example-Based Machine Translation (EBMT) proposed by Nagao. Japanese adnominal particles are important because: (1) they are frequent function words; (2) to translate them into English is difficult because their translations are diversified; (3) EBMT's effectiveness for adnominal particles suggests that EBMT is effective for other function words, e. g., prepositions of European languages. In EBMT, (1) a database which consists of examples (pairs of a source language expression and its target language translation) is prepared as knowledge for translation; (2) an example whose source expression is similar to the input phrase or sentence is retrieved from the example database; (3) by replacements of corresponding words in the target expression of the retrieved example, the translation is obtained. The similarity in EBMT is computed by the summation of the distance between words multiplied by the weight of each word. The authors' method differs from preceding research in two important points: (1) the authors utilize a general thesaurus to compute the distance between words; (2) the authors propose a weight which changes for every input. The feasibility of our approach has been proven through experiments concerning success rate.

The main objective of this paper is to propose a new top-down subcube allocation scheme which has complete subcube recognition capability with quick response time. The proposed subcube allocation scheme, called Heuristic Subcube Allocation (HSA) strategy, is based on a heuristic and undirected graph, called Subcube (SC)-graph, whose vertices represent the free subcubes, and edge represents inter-relationships between free subcubes. It helps to reduce the response time and internal/external fragmentation. When a new subcube is released, the higher dimension subcube is generated by the cycle detection in the SC-graph, and the heuristic is used to reduce the allocation time and to maintain the dimension of the free subcube as high as possible. It is theoretically shown that the HSA strategy is not only statically optimal but also it has a complete subcube recognition capability in a dynamic environment. Extensive simulation results show that the HSA strategy improves the performance and significantly reduces the response time compared to the previously proposed schemes.

The problems of cache coherency in multiprocessor systems are directly related to their architectural structures. Small scale multiprocessor systems have focused on the use of bus based memory interconnection networks using centrally shared memory and a sequential consistency model for coherency. This has limited scalability to but a few tens of processors due to the limited bus bandwidth used for both coherency updates and memory traffic. Recently, large scale multiprocessor systems have been proposed that use general interconnection networks and distributed shared memory. These architectures have been proposed using weak consistency models and various directory map schemes to hide the overhead for coherency maintenance within the memory hieratchy, interconnection network or process context switch latencies. The coherency and memory traffic are still maintained over the same interconnection network. In this paper, we present the architecture of a new general purpose medium scale multiprocessor system. This Cache Coherent Multiprocessor System (C2MP), supports distributed shared memory using a general memory interconnection network for memory traffic and a separate bus based coherency interconnection network for coherency maintenance. Through the use of a special directory based coherency protocol and cache oriented distributed coherency controllers, direct cache-to-cache coherency maintenance is performed over the dedicated coherency bus. This minimizes coherency updates to only those processor nodes needing coherency maintenance. An aggressive sequential coherncy model is used, which reduces the hardware penalty to support an ideal sequential consistency programmers model. The system can scale up to 256-512 processors depending on the degree of shared data and is expected to have higher per processor utilization in this range than currently proposed medium and large scale multiprocessor systems. The C2MP system is analyzed utilizing a Generalized Timed Petri-Net model of a processor node. A stochastic model for internode interactions over the general memory interconnection network and coherency bus are used . The model of the proposed architecture is analyzed under steady-state conditions for varying system work load parameters.

First, a number of issues pertaining to analog VLSI implementation of Backpropagation (BP) and Deterministic Boltzmann Machine (DBM) learning algorithms are clarified. According to the results from software simulation, a mismatch between the activation function and derivative generated by independent circuits degrades the BP learning performance. The perfomance can be improved, however, by adjusting the gain of the activation function used to obtain the derivative, irrespective of the original activation function. Calculation errors embedded in the circuits also degrade the learning preformance. BP learning is sensitive to offset errors in multiplication in the learning process, and DBM learning is sensitive to asymmetry between the weight increment and decrement processes. Next, an analog VLSI architecture for implementing the algorithms using common building block circuits is proposed. The evaluation results of test chips confirm that synaptic weights can be updated up to 1 MHz and that a resolution exceeding 14 bits can be attained. The test chips successfully perform XOR learning using each algorithm.

There have been several studies related to a reduction of the amount of computational resources used by Turing machines. As consequences, Linear speed-up theorem", tape compression theorem" and reversal reduction theorem" have been obtained. In this paper, we discuss a leaf reduction theorem on alternating Turing machines. Recently, the result that one can reduce the number of leaves by a constant factor without increasing the space complexity was shown for space- and leaf-bounded alternating Turing machines. We show that for time- and leaf-bounded alternating Turing machines, the number of leaves can be reduced by a constant factor without increasing time used by the machine. Therefore, our result says that a constant factor on the leaf complexity does not affect the power of time- and leaf-bounded alternating Turing machines.

This paper describes the future perspective of automatic telephone interpretation using a multimedia intelligent communication network. The need for language interpretation over a telecommunication system creates a strong drive toward integrating information modalities for voice, image, data, computation and conferencing into modern systems using the capability of language interpretation. An automatic telephone interpretation system will solve the problems of language differences in international human-to-human communication. The future prospective of advanced multimedia language communication will be stated as the versatile application of an integrated intelligent network.