There have been several interesting investigations on the space functions constructed by one-dimensional or two-dimensional Turing machines. On the other hand, as far as we know, there is no investigation about the space functions constructed by three-dimensional Turing machines. In this paper, we investigate about space constructibility by three-dimensional deterministic Turing machines with cubic inputs, and show that the functions log*n and log(k)n, k1, are fully space constructible by these machines.

Binary decision diagrams (BDD's) are graph representations of Boolean functions, and at the same time they can be regarded as a computational model. In this paper, we discuss relations between BDD's and other computational models and clarify the computational power of BDD's. BDD's have the property that each variable is examined only once according to a total order of the variables. We characterize families of BDD's by on-line deterministic Turing machines and families of permutations. To clarify the computational power of BDD's, we discuss the difference of the computational power with respect to the way of reading inputs. We also show that the language TADGAP (Topologically Arranged Deterministic Graph Accessibility Problem) is simultaneously complete for both of the class U-PolyBDD of languages accepted by uniform families of polynomial-size BDD's and the clas DL of languages accepted by log-space bounded deterministic Turing machines. From the results, we can see that the problem whether U-PolyBDD U-NC1 is equivalent to a famous open problem whether DL U-NC1, where U-NC1 is the class of languages accepted by uniform families of log-depth constant fan-in logic circuits.

It is an important problem whether or not we can reject the disturbances from distributed parameter circuit. In order to analyze this problem structurally, it is necessary to investigate the basic equation of distributed parameter circuit in the framework of state space. Since the basic equation has two parameters for time and space, the state value belongs to an infinite-dimensional space. In this paper, the disturbance-rejection problems with incomplete state feedback and/or incomplete state feedback and feedforward for infinite-dimensional systems are studied in the framework of geometric approach. And under certain assumptions, necessary and/or sufficient conditions for these problems to be solvable are proved.

The Alopex algorithm is presented as a universal learning algorithm for neural networks. Alopex is a stochastic parallel process which has been previously applied in the theory of perception. It has also been applied to several nonlinear optimization problems such as the Travelling Salesman Problem. It estimates the weight changes by using only a scalar cost function which is measure of global performance. In this paper we describe the use of Alopex algorithm for solving nonlinear learning tasks by multilayer feed-forward networks. Alopex has several advantages such as, ability to escape from local minima, rapid algorithmic computation based on a scalar cost function and synchronous updation of weights. We present the results of computer simulations for several tasks, such as learning of parity, encoder problems and the MONK's problems. The learning performance as well as the generalization capacity of the Alopex algorithm are compared with those of the backpropagation procedure, and it is shown that the Alopex has specific advantages over backpropagation. An important advantage of the Alopex algorithm is its ability to extract information from noisy data. We investigate the efficacy of the algorithm for faster convergence by considering different error functions. We show that an information theoretic error measure shows better convergence characteristics. The algorithm has also been applied to more complex practical problems such as undersea target recognition from sonar returns and adaptive control of dynamical systems and the results are discussed.

This paper investigates the properties of synchronized alternating one-way multicounter machines (lsamcm's) which operate in real time (lsamcm-real's) and whose leaf-sizes are bounded by a constant or some function of the length of an input. Leaf-size reflects the number of processors which run in parallel in scanning a given input. We first consider the hieracrchies of lsamcm-real's based on the number of counters and constant leaf-sizes. We next show that lsamcm-real's are less powerful than lsamcm's which operate in linear time when the leaf-sizes of these machines are bounded by a function L(n) such that limn[L(n) log n/n]0 and L(n)2.

This paper proposes a new type of transfer system, called Similarity-driven Transfer System (or SimTran), which uses an example-based approach to the transfer phase of MT. In this paper, we describe a method for calculating similarity, a method for searching the most appropriate set of translation rules, and a method for constructing an output structure from those selected rules. Further, we show that SimTran can use not only translation examples but also syntax-based translation rules used in conventional transfer systems at the same time.

This paper presents an experimental environment of an intelligent tutoring system called EXPITS. In this environment, users learn functions and the structure of the intelligent tutoring system and characteristics of knowledge processing. EXPITS provides facilities for investigating internal processes and internal states of the intelligent tutoring system. These facilities include visualization tools and controllers of internal processes. Because the internal states and behavior of ITS depend on student's understanding states, one cannot get total understanding of ITS without information about student's knowledge states. To solve this problem, we introduce a pseudo student which simulates a human student in order to visualize explicitly all information which affects ITS behavior. Target users of EXPITS are school teachers, who are users of intelligent tutoring systems, university students who are studying artificial intelligence and postgraduate students who are specially studying intelligent tutoring systems. We have designed EXPITS to achieve different learning objectives for these three kinds of users. The learning objective for school teachers is to understand the differnce between intelligent tutoring systems and traditional CAI systems. University students are expected to understand characteristics of knowledge processing and rule based systems. Lastly, EXPITS provides postgraduate students who are studying intelligent tutoring systems with a test bed for examining ability and efficiency of the system in different configurations by changing parameters and by replacing constituents of the system. To achieve these purposes, EXPITS has experimental facilities for the following four themes; relationship between the domain knowledge representation method and teaching activities, the selection method of teaching paradigms, relationship between problem solving processes and teaching activities, and student modeling.

Until now, in a communication system which deals with multiple processes, system behavior has been described by a fixed number of processes. The state reachability problem for specified processes was generally deliberated within a pre-defined number of processes, and was analyzed by essentially searching for all possible behaviors. However, in a system whose number of processes is arbitrary, a given state which is not reachable in some situations which consists of a small number of processes might be reachable in another situation which consists of a larger number of processes. This article discusses the above problem, assuming that the behavior of a system is described by an arbitrary number of processes. After discussing the relationship between our model and the Petri net model, we clarify the properties between the set of reachable states and the number of processes involved in the system, and show an algorithm to obtain a sufficient number of processes for resolving the reachability problem.

This letter presents an algorithm named SPM which generates test patterns for single stuck-at faults in synchronous sequential circuits based on a product machine traversal method. The new idea presented in this letter is partitioned image computation combined with a mixed breadth-first/depth-first search. Image computation is carried out in partitioned manner by substituting constant logical values to some input variables. This brings about significant reduction in storage requirement during image computation. A test generator based on SPM achieved 100% fault efficiency for the ISCAS'89 benchmark circuits with not more than 32 flip-flops.

This paper presents a Reconfigurable Machine (RM). capable of efficiently implementing a wide range of computationlly complex algorithms. Its highly flexble architecture combining FPGA's with RAM's supports a wide range of applications. Since its "gate-level programmability" allows us to implement various kinds of parallel processing techniques, RM provides a perfomance comparable to exising "special-purpose" engines. The in-circuit reconfiguration capability of FPGA's is used to reload several kinds of configuration data during power on. Thus, RM behaves itself like a general-purpose computer applicable to various kinds of applications by loading programs. A Reconfigurable Machine-(RM-) has been built as the first prototype incorporating five FPGA's and four SRAM memory banks. RM- has been applied to a multiple-delay Logic Simulator (LSIM). Employing pipeline architecture, LSIM has achieved a perfomance of l million gate events per second at 4MHz. The concept of RM is the best solution to the trade-offs between general-purpose machines and special-purpose ones. RM will be a hardware platform accelerating a wide range of applications, also offering an interesting problem in high-level synthesis.

The character binarization method MTC is developed for enhancing the recognition of characters in general outdoor images. Such recognition is traditionally difficult because of the influence of illumination changes, especially strong shadow, and also changes in character, such as apparent character sizes. One way to overcome such difficulties is to restrict objects to be processed by using strong hypotheses, such as type of object, object orientation and distance. Several systems for automatic license plate reading are being developed using such strong hypotheses. However. their strong assumptions limit their applications and complicate the extension of the systems. The MTC method assumes the most reasonable hypotheses possible for characters: they occupy plane areas, consist of narrow lines, and external shadow is considerably larger than character lines. The first step is to eliminate the effect of local brightness changes by enhancing feature including characters. This is achieved by applying mathematical morphology by using a logarithmic function. The enhanced gray-scale image is then binarized. Accurate binarization is achieved because local thresholds are determined from the edges detected in the image. The MTC method yields stable binary results under illumination changes, and, consequently, ensures high character reading rates. This is confirmed with a large number of images collected under a wide variety of weather conditions. It is also shown experimentally that MTC permits stable recognition rate even if the characters vary in size.

Reactive systems respond to internal or external stimuli and act in an event-driven manner. It is generally difficult to specify a complex reactive systems' behavior using conventional state machine formalism. One reason is that actual reactive systems are usually formed by combining plural state-machince that behave concurretly. This paper presents the State Diagram Matrix (SDM) which is a visual and hierarchical formalism of such a reactive system's behavior. SDM has two concepts. The first is matrix plane description on which 3-dimensional state space is projected. The second is state abstraction for hierarchical state-machine definition. Understandability and reliability of control software was improved as a consequence of adopting SDM for specifying disk-subsystem control requirements. The development support functions of SDM using a workstation are also described.

There have been several studies related to a reduction of the amount of computational resources used by Turing machines. As consequences, linear speed-up theorem" tape compression theorem", and reversal reduction theorem" have been obtained. In this paper, we consider reversal- and leaf-bounded alternating Turing machines, and then show that the number of leaves can be reduced by a constant factor without increasing the number of reversals. Thus our results say that a constant factor on the leaf complexity does not affect the power of reversal- and leaf-bounded alternating Turing machines

This paper describes the learning performance of the deterministic Boltzmann machine (DBM), which is a promising neural network model suitable for analog LSI implementation. (i) A new learning procedure suitable for LSI implementation is proposed. This is fully-on-line learning in which different sample patterns are presented in consecutive clamped and free phases and the weights are modified in each phase. This procedure is implemented without extra memories for learning operation, and reduces the chip area and power consumption for learning by 50 percent. (ii) Learning in a layer-type DBM with one output unit has characteristic local minima which reduce the effective number of available hidden units. Effective methods to avoid reaching these local minima are proposed. (iii) Although DBM learning is not suitable for mapping problems with analog target values, it is useful for analog data discrimination problems.

The recent non von Neumann chip architectures are mainly classified into the AI architecture and the neural architecture. We focus on these two categories, and introduce the representatives each with a brief history. The AI chip architecture is difficult to escape essentially from the von Neumann architecture as far as it is language-oriented. The neural architecture, however, may yield an essentially new computer architecture, when the new device technologies will support it. In particular, the optoelectronics and the quantum electronics will provide a lot of powerful technologies.

A strictly nonblocking 88 matrix switch was designed and fabricated using silica-based planar lightwave circuits (PLC) on a silicon substrate. The average insertion loss was 11 dB in the TE mode and 11.3 dB in the TM mode. The average switch element extinction ratio was 16.7 dB in the TE mode and 17.7 dB in the TM mode. The accumulated crosstalk was estimated to be 7.4 dB in the TE mode and 7.6 dB in the TM mode. The driving power of the phase shifter required for switching was about 0.5 W and the polarization dependence of the switching power was 4%. The switching response time was 1.3 msec. The wavelength range with a switch extinction ratio of over 15 dB was 1.31 µm30 nm.

This paper describes a single-bit parallel processor specified to Boltzmann Machine. The processor has SIMD (Shingle Instruction Multiple Data stream) type parallel architecture and every processing element (PE) has a single-bit ALU and a local memory storing connected weights between neurons. Features of the processor are large scale parallel processing a number of the simple single-bit PEs and effective expansion realized by multiple chips connected simple bus lines. Moreover, it is enhanced that the processing speed can be independent of the number of the neurons. We designed the PE using 1.2 µm CMOS process standard cells and confirmed the high performance using CAD simulations.

Asynchronous machines are a topic of great interest in the research area of actuators. Due to the complexity of these systems and to the required performance, the modelling and control of asynchronous machines are complex questions. Problems arise when the control goals require accurate descriptions of the electric machine or when we need to identify some electrical parameters; in the models employed it becomes very hard to take into account all the phenomena involved and therefore to make the error amplitude adequately small. Moreover, it is well known that, though an efficient control strategy requires knowledge of the flux vector, direct measurement of this quantity, using ad hoc transducers, does not represent a suitable approach, because it results in expensive machines. It is therefore necessary to perform an estimation of this vector, based on adequate dynamic non-linear models. Several different strategies have been proposed in literature to solve the items in a suitable manner. In this paper the authors propose a neural approach both to derive NARMAX models for asynchronous machines and to design non-linear observers: the need to use complex models that may be inefficient for control aims is therefore avoided. The results obtained with the strategy proposed were compared with simulations obtained by considering a classical fifth-order non-linear model.

In this paper, a synthesizing method is proposed for the design of discrete-time cellular neural networks for binary image processing. Based on the theory of digital-logical design paradigm of threshold logic, the template parameters of the discrete-time cellular neural network for a prescribed binary image processing problem are calculated. Application examples including edge detection, connected component detection, and hole filling are given to demonstrate the merits and limitations of the proposed method. For a given realization of the parameters of the cloning template, a guideline for the selection of the offset Ic for maximum error tolerance is also considered.

In this paper, we propose an extended LR parsing algorithm, called LR parsing with a category reachability test (the LR-CRT algorithm). The LR-CRT algorithm enables a parser to efficiently recognize those sentences that belong to a specified grammatical category. The key point of the algorithm is to use an augmented LR parsing table in which each action entry contains a set of reachable categories. When executing a shift or reduce action, the parser checks whether the action can reach a given category using the augmented table. We apply the LR-CRT algorithm to improve a speech recognition system based on two-level LR parsing. This system uses two kinds of grammars, inter- and intra-phrase grammars, to recognize Japanese sentential speech. Two-level LR parsing guides the search of speech recognition through two-level symbol prediction, phrase category prediction and phone prediction, based on these grammars. The LR-CRT algorithm makes possible the efficient phone prediction based on the phrase category prediction. The system was evaluated using sentential speech data uttered phrase by phrase, and attained a word accuracy of 97.5% and a sentence accuracy of 91.2%