This paper proposes a masked data transferring method for the write-back controlled disk cache system employing a fixed-length recording disk drive, enabling data transfer of discontinuous sectors on the same track between the cache and the disk. This paper also evaluates the method. In write-back controlled disk cache sytems, random write requests cause dirty data (write-pending data on a cache) on discontinuous areas on the cache. It is likely that several sectors on the same track become dirty. These dirty sectors must be written onto the disk according to the cache management scheme. In conventional data transferring methods between a disk cache and a disk drive, plural sectors can be transferred in one single operation when the sectors are adjacent, but discrete sectors must be transferred by individual operations. In the methods, an address of the head sector and number of sectors to be transferred are given to the transfer unit. For example, when two sectors on the same track are located closely but not adjacently, and data transfer is requested for those two sectors, the transfer operation for the second sector must be prepared after the first transfer had completed and before the second sector arrives under the disk head. Although the time for the head to pass by the uninterested sector is often too short for the software overhead for the first transfer to be completed and the second transfer to be prepared, which leads to an unwanted extra rotation of the disk. With the masked transferring method proposed in this paper, the micro program creates a bit-map specifying the target sectors to be transferred and passes it to the data transfer unit, enabling to transfer the discontinuous sectors without latency. The method was evaluated using OLTP warkloads. Results show an improvement in random I/O throughput of between 8% and 27%. The masked transferring method is adopted in Hitachi's A-6521 disk subsytems, shipped since December 1993.

Cellular Neural Networks (CNNs) are nonlinear dynamic array processors with mainly local interconnections. In most of the applications, the local interconnection pattern, called cloning template, is translation invariant. In this paper, an optimal ring-coding method for rotation invariant description of given set of objects, is introduced. The design methodology of the templates based on the ring-codes and the synthesis of CNN analogic algorithms to detect standing and moving objects in a rotationally invariant way, discussed in detail. It is shown that the algorithms can be implemented using the CNN Universal Machine, the recently invented analogic visual microprocessor. The estimated time performance and the parallel detecting capability is emphasized, the limitations are also thoroughly investigated.

The overall performance of a shared-memory, common bus multiprocesser system can be seriously affected by useless coherence-related actions. This occurs, in particular, when a private data block of a process becomes resident in more than one cache as a consequence of the migration of the owner process. We introduce a hardware solution to eliminate these useless shared copies, and show how this technique can be applied to a specific coherence protocol. Two extreme workload conditions are properly selected to evaluate the performance of a multiprocessor system.

In this paper, a new optimum input encoding algorithm with m-out-of-2m code which is called Half-Hot Code is presented. By applying Half-Hot Code to the input encoding in PLA-based digital system, the logic functions of the system turn out to be unate functions, thus, the number of bit-lines of PLA may be reduced. The proposed method further reduces the number of product-lines of PLA optimally. In this code assignment procedure, computed Boolean subspaces satisfying suggeset two conditions are assigned to each partitioned subset of digital input variables which are obtained by disjoint minimization or other techniques. As an experiment to evaluate the method, the state assignment for finite state machines of two-lavel implementation is considered. Specifically, the proposed Half-Hot Code assignment is compared with arbitrary Half-Hot Code assignment. The results show that the optimum encoding is superior to an arbitrary assignment up to about 24% in the number of product-lines of PLA.

Intelligent Tutoring Systems (ITS) represents a wide class of computer based tutoring systems, designed with an extensive use of the technology of modern Artificial Intelligence. Successful applications of various expert systems and other knowledge based systems of AI gave rise to a new wave of interests to ITS. Yet, many authors conclude that practically valuable achievements of ITS are rather modest despite the relatively long history of attempts to use knowledge based systems for tutoring. It is advocated in this paper that some basic obstacles for designing really successful ITS are due to the lack of well understood and sound models of the education process. The paper proposes to overcome these problems by borrowing the required models from AI and adjacent fields. In particular, the concept of Learning Levels from AI might be very useful both for giving a valuable retrospective analysis of computer based tutoring and for suggestion of some perspective directions in the field of ITS.

This work is concerned with a dynamic analysis of complex uniplanar guide-wave structures for MMICs at millimeter-wave frequencies. The enhanced spectral domain approach is effectively used to model such uniplanar structures with trapezoidal conducting strips involving microshielding enclosures. A wide range of line propagation and impedance characteristics is obtained for slotline and coplanar waveguide (CPW). The effect of different conductor profiles on line characteristics is discussed in detail. Results show an excellent agreement with other works. A class of dispersion-related curves are presented for design consideration.

This paper establishes a relationship among the accepting powers of deterministic, nondeterministic, and alternating one-way auxiliary pushdown automata, for any tape bound below n. Some other related results are also presented.

Computational approaches to concept formation often share a top-down, incremental, hill-climbing classification, and differ from each other in the concept representation and quality criteria. Each of them captures part of the rich variety of conceptual knowledge and many are well suited only when the object-attribute distribution is not sparse. Formal concept analysis is a set-theoretic model that mathematically formulates the human understanding of concepts, and investigates the algebraic structure, Galois lattice, of possible concepts in a given domain. Adopting the idea of representing concepts by mutual closed sets of objects and attributes as well as the Galois lattice structure for concepts from formal concept analysis, we propose an approach to concept formation and develop OSHAM, a method that forms concept hierarchies with high utility score, clear semantics and effective even with sparse object-attribute distributions. In this paper we describe OSHAM, and in an attempt to show its performance we present experimental studies on a number of data sets from the machine learning literature.

In this paper, we present a method for extracting the Japanese printed characters from unformatted document images. This research takes into account the multiple general features specific to the Japanese printed characters. In our method, these features are thought of as the constraints for the regions to be extracted within the constraint satisfaction approach. This is achieved by minimizing a constraint function estimating quantitative satisfaction of the features. Our method is applicable to all kinds of the Japanese documents because it is no need of a priori knowledge about the document layout. We have favorable experimental results for the effectiveness of this method.

Some CMOS gates are topologically asymmetric in inputs, even though they are logically symmetric. It implies a possibility to reduce power consumption by optimizing signal assignment to the inputs. In this study we theoretically derive power consumption of 2-input NAND gate based on transition probability of input signals, with taking into account charging current due to an internal node. We also propose a signal assignment method to input terminals for reducing power consumption reduction by extending our method for large circuits, and demonstrate the effect of power consumption reduction by the present method.

The Manchester Dataflow Machine (MDFM) works with tasks of size equal to one single instruction. This fine granularity aims at exploring all parallelism at the instruction level. However, this project decision increases the instruction communication cost, which ends up to jam the interconnection network and reduces the system performance. One way to skirt this problem is to adopt variable size tasks instead of working with such small task size. In this paper, in order to study whether or not the usage of such variable size tasks in the MDFM architecture contributes to the improvement of the performance, some simulations by toy programs take place. In the simulation, variable size tasks are realized by packing the sequential instruction stretches into one task. To manage this packing, the Sequential Block (SB) technique is developed. The simulation of those packed and unpacked programs give an outline of advantages and disadvantages of working with variable size tasks, and how the SB technique should be implemented in the system.

Connection Admission Control (CAC) is a key part of traffic control and still leaves several challenging problems peculiar to ATM networks. One of these problems is how to assign sufficient bandwidth for any cell arrival process that satisfies the source traffic descriptor values specified by negotiation between the network and a user at the connection setup. Because the source traffic descriptor cannot describe the actual source traffic characteristics completely, it has already been studied extensively that how to estimate sufficient bandwidth under the assumption that the actual traffic parameter values in the source traffic descriptor are equal to the negotiated values. This paper extends the studies in the literature to how to estimate sufficient bandwidth only assuming that the actual values satisfy the negotiated values, that is the actual values is less than or equal to the negotiated values. We show the sufficient condition for negotiated source traffic descriptors ensuring that the cell-loss ratio calculated from the negotiated values is always the upper-bound of the actual cell-loss ratio. Using this condition, we propose a CAC that can guarantee cell-loss ratio objective so far as a user satisfies the source traffic descriptor values.

GaAs-based micromachining is a very attractive technique for integrating mechanical structures and active optical devices, such as laser diodes and photodiodes. For monolithically integrating mechanical parts onto laser diode wafers, the micromachining technique must be compatible with the laser diode fabrication process. Our micromachining technique features three major processes: epitaxitial growth (MOVPE) for both the structural and sacrificial layers, reactive dry-etching by chlorine for high-aspect, three-dimensional structures, and selective wet-etching by peroxide/ammonium hydroxide solution to release the moving parts. These processes are compatible with laser fabrication, so a cantilever beam structure can be fabricated at the same time as a laser diode structure. Furthermore, a single-crystal epitaxial layer has little residual stress, so precise microstructures can be obtained without significant deformation. We fabricated a microbeam resonator sensor composed of two laser diodes, a photodiode, and a micro-cantilever beam with an area of 400700 µm. The cantilever beam is 3 µm wide, 5 µm high, and either 110µm long for a 200-kHz resonant frequency or 50 µm long for a 1-MHz resonant frequency. The cantilever beam is excited by an intensity-modulated laser beam from an integrated excitation laser diode; the vibration signal is detected by a coupled cavity laser diode and a photodiode.

Automatic alignment of bilingual texts is useful to example-based machine translation by facilitating the creation of example pairs of translation for the machine. Two main approaches to automatic alignment have been reported in the literature. They are lexical approach and statistical approach. The former looks for relationships between lexical contents of the bilingual texts in order to find alignment pairs, while the latter uses statistical correlation between sentence lengths of the bilingual texts as the basis of matching. This paper describes a combination of the two approaches in aligning Japanese-Cinese bilingual texts by allowing kanji contents and sentence lengths in the texts to work together in achieving an alignment process. Because of the sentential structure differences between Japanese and Chinese, matching at the sentence level may result in frequent matching between a number of sentences en masses. In view of this, the current work also attempts to create shorter alignment pairs by permitting sentences to be matched with clauses or phrases of the other text if possible. While such matching is more difficult and error-prone, the reliance on kanji contents has proven to be very useful in minimizing the errors. The current research has thus found solutions to problems that are unique to the present work.

In current teleteaching systems, video conferencing systems have been used to transmit a motion video from a teacher's site. A video that captures a teacher or his or her chalkboard is transmitted to a remote site through a communication channel. Since the resolution of the video is not very high, a camera captures either a teacher or a chalkboard, but not both at the same time. Thus, remote students have difficulty in obtaining realistic sensation. Another approach to realizing teleteaching is to use a computer-based desktop conferencing system that supports a motion video and a computer-based shared chalkboard. In this approach, a teacher has to use a mouse or a handwriting tablet for input, and therefore cannot use a real chalkboard. Moreover, the teacher cannot use gestures to remote students. This paper presents a multimedia teleteaching system that integrates an electronic whiteboard with a multimedia desktop conferencing system for providing realistic sensation to remote students. The system provides two-way communication of a video and a computerized chalkboard. A teacher uses an electronic whiteboard as a real whiteboard using direct manipulation, and transmits his or her gestures to remote students by using video communication. The system provides dual views; one view is for teacher's gestures and the other is for chalkboard contents. By providing the dual views, the system can transmit teacher's gestures all the time. Since chalkboard contents are processed and displayed as computer data, students can see them clearly. With the computerized chalkboard, a teacher or a student can zoom contents, input data written on a paper using a scanner, or add annotation.

There are two approaches to implementing the international standard video coding algorithms such as H.261 and MPEG: a programmable DSP approach and a building block approach. The advantages and disadvantages of each are discussed here in detail, and the video coding algorithms and required throughput are also summarized. For more complex standard such as MPEG-, VLSI architecuture became more sophisticated. The DSP approach incorporates special processing engines and the building block approach integrates general-purpose microprocessors. Both approaches are capable of MPEG- NTSC coding in a single chip. Reduction of power consumption is a key issue for video LSIs. Architectures and circuits that reduce the supply voltage while maintaining throughput are summarized. A 0.25-µm, 3-GOPS, 0.5-W, SIMD-VSP for portable MPEG- systems could be made by using architecture-driven voltage scaling as well as feature-size scaling and SOI devices.

As to the method of multi-layer testing, up to now, the testing system (called PROVES) which testes effectively each N-layer protocol implement of SUT (System Under Test) using the functions of derail-points located between N-layer and (N+1)-layer protocol implements in a test system has been proposed. The test logic programs, which are embedded in the derail-points of the test system, play an important role to realize the protocol error test sequences in the test system. Namely, they modify, add, or delete the correct protocol commands/responses output from the protocol implement part of the lest system, sends these erroneous commands/responses to SUT and observes the output from SUT. This paper proposes the method of validating the correctness of test logic program using the structural properties of Petri nets without coding the test logic programs, where correctness means that the desired output can be obtained by sending or receiving the commands/responses within a constant time under the initial conditions determined uniquely by the test system and SUT. According to our experiment, it is seen that almost all of the logical errors included in the test logic programs used for the experiment can be detected by this method.

The newly developed high speed DRAMs are introduced and their innovative circuit techniques for achieving a high data bandwidth are described; the synchronous DRAM, the cache DRAM and the Rambus DRAM. They are all designed to fill the performance gap between MPUs and the main memory of computer systems, which will diverge in '90s. Although these high speed DRAMs have the same purpose to increase the data bandwidth, their approaches to accomplish it is different, which may in turn lead to some advantages or disadvantages as well as their fields of applications. The paper is intended not only to discuss them from technical overview, but also to be a guide to DRAM users when choosing the best fitting one for their systems.

A 250-MIPS, 125-MFLOPS peak performance processing element (PE), which is being developed for an on-chip multiprocessor, has been modeled and evaluated. The PE includes the following new architecture components: an FPU shared by several IUs in order to increase the efficiency of the FPU pipelines, an on-chip data cache with a prefetch mechanism to reduce clock cycles waiting for memory, and an interface to high speed DRAM, such as Rambus DRAM and Synchronous DRAM. As a result, a PE model with an FPU shared by four or eight IUs causes only 10% performance reduction compared to a model with an un-shared FPU model while saving the cost of three FPUs. Furthermore, a PE model with prefetch operates 1.2 to 1.8 times faster than a model without prefetch at 250-MHz clock rate when the Rambus DRAM is connected. It becomes clear that this PE architecture can bring a high effective performance at over 250-MHz, and is cost-effective for the on-chip multiprocessor.

The present study describes using the state transition type of drawing understanding framework to construct a multi-purpose drawing understanding system. This new system employs an understanding process that complies with the understanding rules, which are easily obtained by the user. The same set of user-provided rules must be used for the same type of target drawings, but for slightly different ones, fine tuning is required to obtain understanding rules. To overcome this inherent drawback in constructing drawing understanding systems, we extended the system using a newly constructed understanding rule generating support system. The resultant integrated system is based on a man-machine cooperation type interface, and can automatically generate rules from user-provided simple interactions using a graphical user interace (GUI). To obtain efficient rule generation, the system employs an inductive inference method as a learning algorithm. Map-drawing experiments were successfully carried out, and an evaluation based on a rule leaning error criterion subsequently revealed an efficient rule generation process.