Traditional cellular networks suffer the so-called “cell-edge problem” in which the user throughput is deteriorated because of pathloss and inter-cell (co-channel) interference. Recently, Base Station Cooperation (BSC) was proposed as a solution to the cell-edge problem by alleviating the interference and improving diversity and multiplexing gains at the cell-edge. However, it has minimal impact on cell-inner users and increases the complexity of the network. Moreover, static clustering, which fixes the cooperating cells, suffers from inter-cluster interference at the cluster-edge. In this paper, dynamic fractional cooperation is proposed to realize dynamic clustering in a shared RRU network. In the proposed algorithm, base station cooperation is performed dynamically at cell edges for throughput improvement of users located in these areas. To realize such base station cooperation in large scale cellular networks, coordinated scheduling and distributed dynamic cooperation are introduced. The introduction of coordinated scheduling in BSC multi-user MIMO not only maximizes the performance of BSC for cell-edge users but also reduces computational complexity by performing simple single-cell MIMO for cell-inner users. Furthermore, the proposed dynamic clustering employing shared RRU network realizes efficient transmission at all cell edges by forming cooperative cells dynamically with minimal network complexity. Owing to the combinations of the proposed algorithms, dynamic fractional cooperation achieves high network performance at all areas in the cellular network. Simulation results show that the cell-average and the 5% cell-edge user throughput can be significantly increased in practical cellular network scenarios.

In this paper, we consider the signal processing algorithm on each subcarrier for the downlink of Multi-User Multiple-Input Multiple-Output Orthogonal Frequency Division Multiplexing (MU-MIMO OFDM) system. A novel transmit scheme is proposed for the cancellation of Inter-User Interference (IUI) at the Base Station (BS). The improved performance of each user is obtained by optimizing the transmit scheme on each subcarrier, where the Particle Swarm Optimization (PSO) algorithm is employed to solve the constrained nonlinear optimization problem. Compared with the conventional Zero Forcing Dirty Paper Coding (ZF-DPC) having only single receive antenna at each Mobile Station (MS), the proposed scheme also applies the principle of DPC to cancel the IUI, but the MS users can be equipped with multiple receive antennas producing their increased receive SNR's. With the Channel State Information (CSI) being known at the BS and the MS, the eigenvalues for all the user channels are calculated first and then the user with the maximum eigenvalue is selected as the 1-st user. The remaining users are ordered and sequentially processed, where the transmit weights are generated from the previously selected users by the Particle Swarm Optimization (PSO) algorithm which ensures the transmit gain for each user as large as possible. The computational complexity analysis, BER performance and achievable sum-rate analysis of system verify the effectiveness of the proposed scheme.

This paper presents a verification and analysis tool set for embedded systems. Recently, the development scale of embedded systems has been increasing since they are used for mobile systems, automobile platforms, and various consumer systems with rich functionality. This has increased the amount of time and cost needed to develop them. Consequently, it is very important to develop tools to reduce development time and cost. This paper describes a tool set consisting of three tools to enhance the efficiency of embedded system design. The first tool is an integrated tool platform. The second is a remote debugging system. The third is a clock-accurate verification system based on a field-programmable gate array (FPGA) for custom embedded systems. This tool set promises to significantly reduce the time and cost needed to develop embedded systems.

Iterative synthesis methods for making aware of wire congestion are proposed for a multi-context dynamically reconfigurable processor (DRP) with a large number of processing elements (PEs) and programmable-wire connections. Although complex data-paths can be synthesized using the programmable-wire, its delay is long especially when wire connections are congested. We propose two iterative synthesis techniques between a high-level synthesizer (HLS) and the place & route tool to shorten the prolonged wire delay. First, we feed back wire delays for each context to a scheduler in the HLS. The experimental results showed that a critical-path delay was shorten by 21% on average for applications with timing closure problems. Second, we skip the routing and estimate wire delays based on the congestion. The synthesis time was shorten to 1/3 causing delay improvement rate degradation at two points on average.

To improve the quality of wireless communication, transmit/receive diversity techniques in multiple-input multiple-output (MIMO) system have been investigated vigorously. In this paper, we consider an asymmetric MIMO orthogonal frequency division multiplexing (MIMO-OFDM) system, in which the number of transmit antennas is larger than that of receive antennas. In this system, there is a need to achieve the high quality of communication in both low and high mobility scenarios by a single transmit diversity scheme. Recently, as for the advanced diversity schemes based on space time block coding (STBC)/space frequency block coding (SFBC), STBC/STBC-phase shift diversity (PSD) and SFBC-frequency switched transmit diversity (FSTD) have been proposed. However, in these schemes, it is possible that time diversity gain can not be sufficiently obtained especially in the low mobility scenario. Therefore, in this paper, the joint use of grouped phase rotation in time/frequency domain and STBC (GPR-STBC) is proposed to get the larger channel coding gains than other schemes. In this paper, we evaluate the average bit error rate (BER) performance by computer simulation in a comparison with the conventional transmit diversity schemes and discuss the relationship from the viewpoints of BER performance and computational complexity.

This paper presents an interconnect resilient (IR) methodology with maximal interconnect fault tolerance, yield, and reliability for both single and multiple interconnect faults under stuck-at and open fault models. By exploiting multiple routes inherent in an interconnect structure, this method can tolerate faulty connections by efficiently finding alternative paths. The proposed approach is compatible with previous interconnect detection and diagnosis methods under oscillation ring schemes, and together they can be applied to implement a robust interconnect structure that may still provide correct communication even under multiple link faults in Network-on-Chips (NoCs). With such knowledge, designers can significantly improve interconnect reliability by augmenting vulnerable interconnect structures in NoCs. As a result, the experimental results show that alternative paths in NoCs can be found for almost all paths. Hence, the proposed method provides a good way to achieve fault tolerance and reliability/yield improvement.

Visibly pushdown automata (VPA), introduced by Alur and Madhusuan in 2004, is a subclass of pushdown automata whose stack behavior is completely determined by the input symbol according to a fixed partition of the input alphabet. Since it was introduced, VPA have been shown to be useful in various contexts, e.g., as specification formalism for verification and as an automaton model for processing XML streams. However, implementation of formal verification based on VPA framework is a challenge. In this paper, we propose on-the-fly algorithms to test universality and inclusion problems of this automata class. In particular, we first present a slight improvement on the upper bound for determinization of VPA. Next, in order to check universality of a nondeterministic VPA, we simultaneously determinize this VPA and apply the P-automata technique to compute a set of reachable configurations of the target determinized VPA. When a rejecting configuration is found, the checking process stops and reports that the original VPA is not universal. Otherwise, if all configurations are accepting, the original VPA is universal. Furthermore, to strengthen the algorithm, we define a partial ordering over transitions of P-automaton, and only minimal transitions are used to incrementally generate the P-automaton. The purpose of this process is to keep the determinization step implicitly for generating reachable configurations as minimum as possible. This improvement helps to reduce not only the size of the P-automaton but also the complexity of the determinization phase. We implement the proposed algorithms in a prototype tool, named VPAchecker. Finally, we conduct experiments on randomly generated VPA. The experimental results show that the proposed method outperforms the standard one by several orders of magnitude.

Compact design is very important for embedded systems such as wireless sensor nodes, RFID tags and mobile devices because of their limited hardware (H/W) resources. This paper proposes a compact H/W implementation for the KASUMI block cipher, which is the 3GPP standard encryption algorithm. In [8] and [9], Yamamoto et al. proposed a method of reducing the register size for the MISTY1 FO function (YYI-08), and implemented very compact MISTY1 H/W. In this paper we aim to implement the smallest KASUMI H/W to date by applying a YYI-08 configuration to KASUMI, whose FO function has a similar structure to that of MISTY1. However, we discovered that straightforward application of YYI-08 raises problems. We therefore propose a new YYI-08 configuration improved for KASUMI and the compact H/W architecture. The new YYI-08 configuration consists of new FL function calculation schemes and a suitable calculation order. According to our logic synthesis on a 0.11-µm ASIC process, the gate size is 2.99 K gates, which, to our knowledge, is the smallest to date.

The digital logic rewiring technique has been shown to be one of the most powerful logic transformation methods. It has been proven that rewiring is able to further improve some already excellent results on many EDA problems, ranging from logic minimization, partitioning, FPGA technology mappings to final routings. Previous studies have shown that ATPG-based rewiring is one of the most powerful tools for logic perturbation while a graph-based rewiring engine is able to cover nearly one fifth of the target wires with 50 times runtime speedup. For some problems that only require good-enough and very quick solutions, this new rewiring technique may serve as a useful and more practical alternative. In this work, essential elements in graph-based rewiring such as rewiring patterns, pattern size and locality, etc., have been studied to understand their relationship with rewiring performance. A structural analysis on the target-alternative wire pairs discovered by ATPG-based and graph-based engines has also been conducted to analyze the structural characteristics that favor the identification of alternative wires. We have also developed a hybrid rewiring approach that can take the advantages from both ATPG-based and graph-based rewiring. Experimental results suggest that our hybrid engine is able to achieve about 50% of alternative wire coverage when compared with the state-of-the-art ATPG-based rewiring engine with only 4% of the runtime. Through applying our hybrid rewiring approach to the FGPA technology mapping problem, we could achieve similar depth level and look-up table number reductions with much shorter runtime. This shows that the fast runtime of our hybrid approach does not sacrifice the quality of certain rewiring applications.

In multi-cell OFDMA-based networks, co-channel interference (CCI) is inevitable when the frequency reuse scheme is used. The CCI affects the performance of users, especially that of cell edge users. Several frequency reuse schemes and subcarrier allocation algorithms have been proposed to solve the CCI problem. Nevertheless, it is difficult to improve both the cell capacity and the performance of cell edge users since they have a trade-off. In this paper, we propose a new balanced frequency reuse (BFR) as a new frequency partitioning scheme that gives more power to the users in the outer region and allocates more subcarriers to the users in the inner region. In addition, we propose ordering and directional subcarrier allocation (ODSA) for our frequency partitioning proposal to mitigate the CCI effectively when cells have heterogeneous traffic loads. The performance of the proposed BFR with the ODSA algorithm is investigated via analyses and simulations. Performance evaluation shows that the proposed BFR with the ODSA algorithm can increase both the spectral efficiency and the performance of cell edge users if the transmission power is appropriately handled.

Over a correlated flat fading channel, multiple-symbol differential detection can enhance the performance of coded differential phase shift keying (DPSK) systems but with exponential complexity. For iterative decoding schemes, the soft-input soft-output (SISO) multiple-symbol differential sphere decoding (MSDSD) can offer suboptimal performance and its complexity is quadratic with detection length. To further reduce the complexity, this paper proposes a Forward/Backward MSDSD (FB-MSDSD) for coded DPSK systems. The key idea is that the detection interval is split into two subintervals which are processed in the forward and backward directions respectively. Simulation results show that the proposed scheme has almost the same performance and lower complexity when compared with the SISO-MSDSD scheme with the same detection length.

In this paper, we propose an approach to obtaining enhanced performance of the Linpack benchmark on a GPU-accelerated PC cluster connected via relatively slow inter-node connections. For one node with a quad-core Intel Xeon W3520 processor and a NVIDIA Tesla C1060 GPU card, we implement a CPU–GPU parallel double-precision general matrix–matrix multiplication (dgemm) operation, and achieve a performance improvement of 34% compared with the GPU-only case and 64% compared with the CPU-only case. For an entire 16-node cluster, each node of which is the same as the above and is connected with two gigabit Ethernet links, we use a computation-communication overlap scheme with GPU acceleration for the Linpack benchmark, and achieve a performance improvement of 28% compared with the GPU-accelerated high-performance Linpack benchmark (HPL) without overlapping. Our overlap GPU acceleration solution uses overlaps in which the main inter-node communication and data transfer to the GPU device memory are overlapped with the main computation task on the CPU cores. These overlaps use multi-core processors, which almost all of today's high-performance computers use. In particular, as well as using a CPU core for communication tasks, we also simultaneously use other CPU cores and the GPU for computation tasks. In order to enable overlap between inter-node communication and computation tasks, we eliminate their close dependence by breaking the main computation task into smaller tasks and rescheduling. Based on a scheme in which part of the CPU computation power is simultaneously used for tasks other than computation tasks, we experimentally find the optimal computation ratio for CPUs; this ratio differs from the case of parallel dgemm operation of one node.

WSNs (Wireless Sensor Networks) are becoming more widely used in various fields, and localization is a crucial and essential issue for sensor network applications. In this letter, we propose a low-complexity localization mechanism for WSNs that operate in 3D (three-dimensional) space. The basic idea is to use aerial vehicles that are deliberately equipped with anchor nodes. These anchors periodically broadcast beacon signals containing their current locations, and unknown nodes receive these signals as soon as the anchors enter their communication range. We estimate the locations of the unknown nodes based on the proposed scheme that transforms the 3D problem into 2D computations to reduce the complexity of 3D localization. Simulated results show that our approach is an effective scheme for 3D self-positioning in WSNs.

The message passing interface (MPI) broadcast communication commonly causes a severe performance bottleneck in multicore system that uses distributed memory. Thus, in this paper, we propose a novel algorithm and hardware structure for the MPI broadcast communication to reduce the bottleneck situation. The transmission order is set based on the state of each processing node that comprises the multicore system, so the novel algorithm minimizes the performance degradation caused by conflict. The proposed scoreboard MPI unit is evaluated by modeling it with SystemC and implemented using VerilogHDL. The size of the proposed scoreboard MPI unit occupies less than 1.03% of the whole chip, and it yields a highly improved performance up to 75.48% as its maximum with 16 processing nodes. Hence, with respect to low-cost design and scalability, this scoreboard MPI unit is particularly useful towards increasing overall performance of the embedded MPSoC.

Orthogonal frequency division multiple access (OFDMA) is adopted as a multiuser access scheme in recent cellular systems such as long term evolution (LTE) and WiMAX. In those systems, the performance improvement on cell-edge users is crucial to provide high-speed services. We propose a new resource allocation scheme based on multiple input multiple output – orthogonal frequency division multiple access – code division multiplexing (MIMO-OFDMA-CDM) to achieve performance improvements in terms of cell-edge user throughput, bit error rate, and fairness among users. The proposed scheme adopts code division multiplexing for MIMO-OFDMA and a modified proportional fairness algorithm for CDM, which enables the fairness among users and a higher throughput. The performance improvements are clarified by theoretical analysis and simulations.

This paper investigates a precoding method in downlink multiuser multiple-input multiple-output (MIMO) transmission with multiple base station (BS) cooperation, where each user device basically feeds back the instantaneous channel state information (CSI) to only the nearest BS, but the users near the cell edge additionally feedback the instantaneous CSI to the second nearest BS among the cooperating BSs. Our precoding method is categorized as a form of multi-cell processing (MCP) [5], in which the transmission information to a user is shared by the cooperating BSs in order to utilize fully the degrees of freedom of the spatial channel, and is based on block diagonalization of the channel matrix. However, since some elements of the channel matrix are unknown, we allow partially non-orthogonal transmission. More specifically, we allow inter-user interference to users with limited instantaneous CSI feedback from the channel where the instantaneous CSIs of those users are not obtained at the BSs. The other sources of inter-user interference are set to zero based on the block diagonalization of the channel matrix. The proposed method more efficiently utilizes the degrees of freedom of the spatial channel compared to the case with full orthogonal transmission at the cost of increased inter-user interference. Simulation results show the effectiveness of the proposed method compared to the conventional approaches, which can accommodate the partial CSI feedback scenario, from the viewpoints of the required transmission power and achievable throughput.

In this paper, a distributed cooperative multicell beamforming algorithm is proposed, and a detail analysis and solving method for instantaneous and statistical channel state information (CSI) are presented. Firstly, an improved distributed iterative beamforming algorithm is proposed for the multiple-input single-output interference channel (MISO IC) scenario which chooses virtual signal-to-interference-and-noise (SINR) as decision criterion to initialize and then iteratively solves the constrained optimization problem of maximizing the virtual SINR for a given level of generated interference to other users. Then, the algorithm is generalized to the multicell date sharing scenario with a heuristics power allocation scheme based on a viewpoint of the layered channel. Finally, the performance is illustrated through numerical simulations.

A finite buffer shared by multiple packet queues is considered. Partitioning the buffer to maximize total throughput is formulated as a resource allocation problem, the solution is shown to be achieved by a greedy incremental algorithm in polynomial time. The optimal buffer allocation strategy is applied to different models for a wireless downlink. First, a set of parallel M/M/1/mi queues, corresponding to a downlink with orthogonal channels is considered. It is verified that at high load, optimal buffer partitioning can boost the throughput significantly with respect to complete sharing of the buffer. Next, the problem of optimal combined buffer allocation and channel assignment problems are shown to be separable in an outage scenario. Motivated by this observation, buffer allocation is considered in a system where users need to be multiplexed and scheduled based on channel state. It is observed that under finite buffers in the high load regime, scheduling simply with respect to channel state with a simply partitioned buffer achieves comparable throughput to combined channel and queue-aware scheduling.

This work addresses the problem of a fast packet retransmission scheme intended for transporting delay-sensitive flows in a Cooperative Diversity (CD) environment. This cooperative fast retransmission scheme exploits the advantages of the CD environment and hybrid Automatic-Repeat-reQuest (ARQ), while allowing retransmission just one time via a cooperating user (i.e., partner) or via both the sender and the partner simultaneously. Complementary link packets are used for the retransmission whose policy can be adjusted on the basis of the qualities of channels among the sender, the partner and the receiver, as well as the application layer protocol data unit size, using the application throughput as the objective. For this scheme, we first derive the application throughput formulas which are then verified via simulations. Next, the CD-based optimized fast retransmission scheme is shown able to achieve better effective throughput (goodput) than other CD-based or non-CD-based ARQ schemes in various Nakagami-m slow-fading environments. As a result, the proposed scheme should be an excellent fast retransmission mechanism for real-time multimedia transport in many CD environments.

In this paper, we propose an iterative minimum mean square error detection with interference cancellation (MMSED-IC) for frequency-domain filtered single carrier (SC)-frequency-division multiple-access (FDMA) uplink transmission. The use of a square-root Nyquist transmit filter reduces the peak-to-average power ratio (PAPR) while increases the frequency-diversity gain. However, if carrier-frequency separation among multiple-access users is kept the same as the one used for the case of roll-off factor α=0 (i.e., brick-wall filter), then the adjacent users' spectra will overlap and multi-user interference (MUI) occurs. The proposed MMSED-IC can sufficiently suppress the MUI from adjacent users while achieving the maximum frequency-diversity gain. We apply the proposed MMSED-IC to a packet access using filtered SC-FDMA, multi-input multi-output (MIMO) multiplexing, and hybrid automatic repeat request (HARQ). It is shown by computer simulation that filtered SC-FDMA with α=1 can achieve higher throughput than orthogonal frequency division multiple access (OFDMA).