While active researches have been continuously made on the ATM switch architectures and the QoS service guarantees, most of them have been treated independently in the past. In this paper, we first explain the architectural requirement on the ATM switches to implement the mechanism of QoS guarantees in the context of ATM congestion control. Then we discuss how a vital link between two should be built, and remaining problems are pointed out.

A large-scale modular multicast ATM switch based on a three-stage Clos network architecture is proposed and its performance is studied in this paper. The complexity of our proposed switch is NN if the switch size is NN. The first stage of the proposed multicast switch consists of n sorting modules, where n=N. Each sorting module has n inputs and n outputs and is responsible for traffic distribution. The second and third stages consist of modified Knockout switches which are responsible for packet replication and switching. Although it is a multipath network, cell sequence is preserved because only output buffers are used in this architecture. The proposed multicast switch has the following advantages: 1) it is modular and suitable for large scale deployment; 2) no dedicated copy network is required since copying and switching are performed simultaneously; 3) two-stage packet replication is used which gives a maximum fan-out of n2; 4) translation tables are distributed which gives manageable table sizes; 5) high throughput performance for both uniform and nonuniform input traffic; 6) self-routing scheme is used. The performance of the switch under uniform and non-uniform input traffic is studied and numerical examples demonstrate that the cell loss probability is significantly improved when the distribution network is used. In a particular example, it is shown that for the largest cell loss probability in the second stage to be less then 10-11, the knockout expander, with the use of the distribution network, needs only be larger than 6. On the other hand, without the distribution network, the knockout expander must be larger than 13.

A new ATM switch architecture, named shared multibuffering, features great advantages on memory access speed for a large switch, and overall size of buffer memories to achieve excellent cell-loss performance. We have developed a 622-Mb/s 88 shared multibuffer ATM switch with multicast functions and hierarchical queueing functions to accommodate 156-Mb/s, 622-Mb/s and 2.4-Gb/s interfaces. Implementation of the shared multibuffer ATM switch is described with respect to the four sorts of 0.8-µm BiCMOS LSIs and ATM switch boards. The switch board/type-1, with C1-LSI, allows to accommodate effectively 156-Mb/s and 622-Mb/s interfaces, which is suitable for an ATM access system. The switch board/type-2, with C2-LSI, can provide multicast functions and accommodate a 2.4-Gb/s interface. By using four switch boards, it is possible to apply them to a 2.4-Gb/s ATM loop system.

Many ATM switching modules with high performance have been proposed and analyzed. A development of a large scale ATM switching system (e.g., used as a central switch) is the key to realization of the broadband ISDN. However, the dimension of ATM switching ICs is limited by the technological and physical constraints on VLSI. A multistage switching configuration is one of the promising configurations for a large scale ATM switch. In this paper, we treat a 3-stage switching configuration with no internal bufferes; i.e., bufferless switches are employed at the first and second stages, and output buffered switches at the third stage. A short-term cell loss probability is analyzed in order to examine the influence of bursty traffic on performance of the bufferless switch used at the first two stages. Furthermore, we propose a 4-stage switching configuration with traffic distributors added at the first stage. This switch provides more paths between a pair of input and output ports than the 3-stage switching configuration mentioned above. A few schemes to distribute cells are compared. It is shown that the distributor successfully reduces the deterioration of cell loss probability due to bursty traffic by splitting incoming cells into several switching modules.