This paper reports our new communication components and downlink tests for realizing 2.65Gbps by utilizing two circular polarizations. We have developed an on-board X-band transmitter, an on-board dual circularly polarized-wave antenna, and a ground station. In the on-board transmitter, we optimized the bias conditions of GaN High Power Amplifier (HPA) to linearize AM-AM performance. We have also designed and fabricated a dual circularly polarized-wave antenna for low-crosstalk polarization multiplexing. The antenna is composed of a corrugated horn antenna and a septum-type polarizer. The antenna achieves Cross Polarization Discrimination (XPD) of 37-43dB in the target X-band. We also modify an existing 10m ground station antenna by replacing its primary radiator and adding a polarizer. We put the polarizer and Low Noise Amplifiers (LNAs) in a cryogenic chamber to reduce thermal noise. Total system noise temperature of the antenna is 58K (maximum) for 18K physical temperature when the angle of elevation is 90° on a fine winter day. The dual circularly polarized-wave ground station antenna has 39.0dB/K of Gain - system-noise Temperature ratio (G/T) and an XPD higher than 37dB. The downlinked signals are stored in a data recorder at the antenna site. Afterwards, we decoded the signals by using our non-real-time software demodulator. Our system has high frequency efficiency with a roll-off factor α=0.05 and polarization multiplexing of 64APSK. The communication bits per hertz corresponds to 8.41bit/Hz (2.65Gbit/315MHz). The system is demonstrated in orbit on board the RAPid Innovative payload demonstration Satellite (RAPIS-1). RAPIS-1 was launched from Uchinoura Space Center on January 19th, 2019. We decoded 1010 bits of downlinked R- and L-channel signals and found that the downlinked binary data was error free. Consequently, we have achieved 2.65Gbps communication speed in the X-band for earth observation satellites at 300 Mega symbols per second (Msps) and polarization multiplexing of 64APSK (coding rate: 4/5) for right- and left-hand circular polarizations.

In the European satellite broadcasting specifications, the symbol rate and the carrier frequency are not regulated. Furthermore, the first generation format DVB-S does not have any control signals. In a practical environment, the received signal condition is not stable due to the imperfect reception environment, i.e., unterminated receiver ports, cheap indoor wiring cables etc. These issues prevent correct detection of the satellite signals. For this reason, the conventional signal detection method uses brute force search for detecting the received signal's cyclostationarity, which is an extremely time-consuming approach. A coarse estimation method of the carrier frequency and the bandwidth was proposed by us based on the power spectrum. We extend this method to create a new method for detecting satellite broadcasting signals, which can significantly reduce the search range. In other words, the proposed method can detect the signals in a relatively short time. In this paper, the proposed method is applied to signals received in an actual environment. Our analysis shows that the proposed method can effectively reduce the detection time at almost a same detection performance.

This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within 10 µs. It is implemented in a 0.18 µm CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8nV/ input referred noise, and 5-dBm IIP3 at 60-mW power consumption. The power detector shows the 35 dB dynamic range for 100 MHz input.