Providing various assistances for design modifications on HDL source codes is important for design reuse and quick design cycle in VLSI CAD. Program slicing is a software-engineering technique for analyzing, abstracting, and transforming programs. We show algorithms for extracting/removing behaviors of specified signals in VHDL descriptions. We also describe a VHDL slicing system and show experimental results of efficiently extracting components from VHDL descriptions.

The analysis of an architecture may provide statistic information on the use of the resources and on the execution time. Some of these information need just a static analysis. Others, such as the execution time, may need dynamic analysis. Moreover as the computation time of behavioral descriptions (control step time unit) and RTL ones (cycle based) may differ a lot, unexpected architectures may be generated by behavioral synthesis. Therefore means to debug the results of behavioral synthesis are required. This paper introduces a new approach to integrate an interactive simulator within a behavioral synthesis tool, thereby allowing concurrent synthesis and simulation. The simulator and the behavioral synthesis are based on the same model. This model allows to link the behavioral description and the architecture produced by synthesis. This paper also discusses an implementation of this concept resulting in a simulator, called AMIS. This tool assists the designer for understanding the results of behavioral synthesis and for architecture exploration. It may also be used to debug the behavioral specification.

This paper proposes a new approach that makes it possible for every undergraduate student to perform experiments of developing a Ipipelined RISC processor within limited time available for the course. The approach consists of 4 steps. At the first step, every student implements by himself/herself a pipelined RISC processor which is based on a given, very simple model; it has separate buses for instruction and data memory ("Harvard architecture") to avoid structural hazard, while it completely ignores data control hazards to make implementation easy. Although it is such a "defective" processor, we can test its functionality by giving object code containing sufficient amount of NOP instructions to avoid hazards. At the second step, NOP instructions are deleted and behavior of the developed processor is observed carefully to understand data and control hazards. At the third step, benchmark problems are provided, and every student challenges to improve its performance. Finally every student is requested to present how he/she improved the processor. This paper also describes a new educational FPGA board ASAver.1 which is useful for experiments from introductory class to computer architecture/system class. As a feasibility study, a 16-bit pipelined RISC processor "ASAP-O" has been developed which has eight 16-bit general purpose registers, a 16-bit program counter, and a zero flag, with 10 essential instructions.

We have developed a method to automatically generate a multi-input-adder circuit for an irregular array of partial products. "FASTOOL," an FIR Filter Automatic Synthesis TOOL for an HDL design environment, is proposed for use with this method and with conventional filter coefficient design programs. Filter design from specifications to the structure of Verilog-HDL has been automated. It is possible for a system designer to quickly perform filter LSI optimization by balancing cost and performance.

The Princeton University Behavioral Synthesis System (PUBSS) performs high-level synthesis on communicating processes. The compiler accepts models written in a subset of VHDL, but performs synthesis using a more specialized model, the behavior FSMs (BFSMs), for synthesis. The simulation semantics of VHDL presents challenges in describing behavior without overly constraining that behavior solely to make the simulation work. This paper describes mismatch between the simulation semantics provided by VHDL and the synthesis semantics required for high-level synthesis and describes how we solved these problems in PUBSS.

We Propose an integrated design and test assistance method for pipelined processors. Our approach generates behavioral-level test environments for pipeline control mechanisms from a machine-readable specification. It includes automatic generation of test programs and behavioral descriptions. Verification can be done by applying logic simulation to both the designers' descriptions and the behavioral descriptions, and then comparing the results. We have implemented an experimental system that enumerates all hazard patterns--instruction patterns that cause pipeline hazards--from the specifications, and generates the test programs and the behavioral descriptions for the pipeline controllers. The test programs cover all of the hazard patterns. The behavioral descriptions can manipulate any instruction stream. Experimental results for several RISC processors show that actual hazard patterns are too numerous to be easily enumerated by hand. Using workstations, our system can generate the test programs that cover all of the patterns, taking a few minutes. Results suggest that the system can be used to evaluate pipeline design.

A design system for a special purpose processor executing algorithms described by high level language is discussed. The system can generate an optimized architecture for the processor and also supply a specialized high level language compiler for the processor. A new optimization procedure is introduced to find effective functional blocks that can contribute to the improvement of performance. Functional blocks are found by simulation of the frequently appearing patterns of execution in the algorithm and used to yield a useful combined instruction.

This paper discusses the trends and future issues in hardware description languages (HDL's) and high-level synthesis systems. First the importance of HDL's and high-level synthesis is described. Then, several HDL's and related CAD systems are briefly introduced. Finally, the requirements to future HDL's and highlevel synthesis systems are discussed from several points of view.