A close correlation between the YBa2Cu3Oy film morphology and location of the (100) MgO substrate during growth by excimer laser ablation was obtained. When the susbtrate was placed inside the fringe portion of the laser plume, the spiral shape was most clearly seen on the entire film surface for both the conventional and eclipse ablation methods. When the substrate was placed outside the plume, the spiral growth was less pronounced. On the other hand, when the substrate was placed inside the plume core, marked deformation of the morphology occurred, and the superconducting critical temperature was lowered. This correlation was explained to some extent by the spatial variation of kinetic energy of the flying growth species.

This paper presents a method for mechanically transforming a parallel algorithm on an original network so that the algorithm can work on a target network. It is assumed that the networks are of cube-type such as the shuffle-exchange network, omega network, and hypercube. Were those networks isomorphic to each other, the algorithm transformation is an easy task. The proposed transformation method is based on a novel graphembedding scheme <φ: δ, κ, π, ψ>. In addition to the dilating operation δ of the usual embedding scheme <φ: δ>, the novel scheme uses three primitive graph-transformation operations; κ (= δ-1) for contracting a path into a node, π for pipelining a graph, and ψ (= π-1) for folding a pipelined graph. By applying the primitive operations, the cube-type networks can be transformed so as to be isomorphic to each other. Relationships between the networks are represented by the composition of applied operations. With the isomorphic mapping φ, an algorithm in a node of the original network can be simulated in the corresponding node(s) of the target network. Thus the algorithm transformation is reduced to routine work.

A new high performance digital signal processor (DSP) that lowers power consumption, reduces chip count, and enables system cost savings for wireless communications applications was developed. The new device contains high performance, hard-wired functionality with a specialized instruction set to effectively implement the worldwide digital cellular standard algorithms, including GSM, PDC and NADC, and also features both full rate and future half rate processing by software modules. The device provides a wider operating voltage ranging from 1.5 V to 5.5 V using 5 V process based on the market requirement of 5 V supply voltage, even though a power supply voltage in most applications will be shifted to 3 V. Several circuits was newly developed to achieve low power consumption and high speed operation at both 5 V and 3 V process using the same data base. The device also features over 50 MIPS of processing power with low power consumption and 100 nA stand-by current at either 3 V or 5 V. One remarkable advantage is a flexible CPU core approach for the future spin-off devices with different ROM/RAM configurations and peripheral modules without requiring any CPU design changes. This paper describes the architecture of a lower power and high speed design with effective hardware and software modules implementations.

This paper discusses an object-oriented approach to temporal multimedia data modeling in OMEGA; a multimedia database management under development at the University of Library and Information Science. An object-orientated approach is necessary to integrate various types of heterogeneous multimedia data, but it has become clear that current object-oriented data models are not sufficient to represent multimedia data, particularly when they are temporal. For instance, the current object-oriented data models cannot describe objects whose attribute values change time-dependently. Also, they cannot represent temporal relationships among temporal multimedia objects. We characterize temporal objects as instances of a subclass of class TimeInterval with the temporal attributes and the temporal relationships. This temporal multimedia data model is designed upward compatible with the ODMG-93 standard object model. To organize a temporal multimedia database, a five temporal axes model for representing temporal multimedia objects is also introduced. The five temporal axes--an absolute, an internal, a quasi-, a physical, and a presentation time axis--are necessary to describe time-dependent properties of multimedia objects in modeling, implementing and use. A concrete example of this organization method is also illustrated.

This paper proposes a new class of error locating codes which corrects random single-bit errors and indicates a location of an erroneous b-bit byte which includes e-bit errors, where 2 e b, called SECSe/bEL codes. This type of codes is very suitable for an application to memory systems constructed from byte-organized memory chips because this corrects random single-bit errors induced by soft-errors and also indicates the position of the faulty memory chips. This paper also gives a construction method of the proposed codes using tensor product of the two codes, i.e., the single b-bit byte error correcting codes and the single-bit error correcting and e-bit error detecting codes. This clarifies lower bounds and error control capabilities of the proposed codes.

The paper describes the architecture and the simulated performances of a memory-based chip that emulates human cortical processing in early visual tasks, such as texture segregation. The featural elements present in an image are extracted by a convolution block and subsequently processed by the cortical chip, whose neurons, organized into three layers, gain relational descriptions (intelligent processing) through recurrent inhibitory/excitatory interactions between both inter-and intra-layer parallel pathways. The digital implementation of this architecuture directly maps the set of equations determining the status of the cortical network to achieve an optimal exploitation of VLSI technology in neural computation. Neurons are mapped into a memory matrix whose elements are updated through a programmable computational unit that implements synaptic interconnections. By using 0.5 µm-CMOS technology, full cortical image processing can be attained on a single chip (2020 mm2 die) at a rate higher than 70 frames/second, for images of 256256 pixels.