Field emission display (FED) is evolving as a promising technique of flat panel displays in the future. In this paper, various carbon based nanostructures are acted as cathode materials for field emission devices. Dendrite-like diamond-like carbon emitters, carbon nanotubes, carbon nanotips are synthesized by microwave plasma chemical vapor deposition. Many factors affect the performance of field emitters, such as the shape, work function and aspect ratio of emission materials. Modified process of carbon based nano-materials for enhancing field emission efficiency are included intrinsic and extrinsic process. These reformations contain the p-type and n-type doping, carburization and new ultra well-aligned carbon nano-materials. It is found that carbon nano-materials grown on micropatterned diode show higher efficiency of FED. In addition, to achieve a low- turn-on field, the novel scheme involving a new fabrication process of gated structure metal-insulator-semiconductor (MIS) diode by IC technology is also presented.

A circuit in which the clock is assumed to be distributed periodically to each individual register though not necessarily to all registers simultaneously, called a semi-synchronous circuit, is expected to achieve higher frequency or a smaller clock tree compared with an ordinary synchronous circuit, called a complete-synchronous circuit. In this paper, we propose a circuit design method that realizes a semi-synchronous circuit with higher frequency by modifying the clock tree of a complete-synchronous circuit. We confirm that the proposed method is easy to incorporate with current practical design environment by designing a four stage pipelined processor compatible with MIPS operation code. The obtained processor circuit is the first semi-synchronous circuit designed systematically with theoretical background.

The plan of High Altitude Platform Station (HAPS) is considered as a revolutionary wireless system plan with several economic and technological advantages over both space- or ground-based counterparts. In this paper, we propose a joint system of terrestrial and HAPS cellular for Wideband-CDMA mobile communication. This system makes the conventional terrestrial W-CDMA cellular area smaller and the remainder area covered by HAPS to increase the total capacity. Furthermore in down link channel, we introduce the polarized wave and doughnut-like radiation. However, in the proposed system, the performance would be dependent on the terminal position especially near the boundary of doughnut-like cell zone. To overcome this, site diversity that uses both signals from terrestrial Base Station and HAPS Base Station is also introduced. To confirm the availability of the proposed system, we evaluate the system performance by computer simulation.

Uniform color spaces are very important in color engineering, image source coding and multimedia information processing. In spite of many efforts have been paid on the subject, however, construction of an exact uniform color space seems difficult until now. Existing approaches mainly used local and heuristic approximations. Moreover, there seemed also certain confusion in definitions of the uniform spaces. In this paper we discuss the issue from a point of view of global Riemannian geometry. The equivalence between global and local definitions of uniform space are shown. Then both an exact and a simplified algorithm are presented to uniformize either a part or the totality of a color space. These algorithms can be expected to find applications in optimal quantization of color information.

Verb phrases are sometimes omitted in natural language (ellipsis). It is necessary to resolve the verb phrase ellipses in language understanding, machine translation, and dialogue processing. This paper describes a practical way to resolve verb phrase ellipses by using surface expressions and examples. To make heuristic rules for ellipsis resolution we classified verb phrase ellipses by checking whether the referent of a verb phrase ellipsis appears in the surrounding sentences or not. We experimented with the resolution of verb phrase elipses on a novel and obtained a recall rate of 73% and a precision rate of 66% on test sentences. In the case when the referent of a verb phrase ellipsis appeared in the surrounding sentences, the accuracy rate was high. But, in the case when the referent of a verb phrase ellipsis did not appear in the surrounding sentences, the accuracy rate was not so high. Since the analysis of this phenomena is very difficult, it is valuable to propose a way of solving the problem to a certain extent. When the size of corpus becomes larger and the machine performance becomes greater, the method of using corpus will become effective.

The strong demand for complex and high performance system-on-a-chip requires high performance microprocessor core and quick turn around design methodology. We have developed 128-bit synthesizable core processor and tile based quick turn around design methodology. It is 200 MHz MIPS compatible processor with 128-bit SIMD extension and is targeted for consumer electronics. We also developed an ASSP including the processor core, SDRAM controller, 2 PCI and 2 MAC mainly for network applications. For SOC development, we developed a tile based design methodology aiming at quick design convergence. The initial RTL design is synthesized and partitioned to several tiles by in-house tiling tool. It promises quick turn around from RTL design to tape out using the concurrency of the back-end design.

Since the impact of the recent rapid penetration of Information Technologies into the society is so tremendous, it is said that IT revolution is coming. Recognizing the above new waves, the Japanese Government is now promoting e-Government programs, and most enterprises are going to depend on the Internet to do their various activities. However, computer criminals, and other threats to security are increasing and becoming serious. Therefore, 'security' is the key for the Internet to be infrastructure of the future society in a true sense. There are many products for security controls, which are not necessarily compatible or interoperable. Interoperability is the basic requirement for infrastructures. In April, 2000, JNSA was organized by about a hundred IT companies. On the other hand, in October, 2000, LINCS was set up in Kogakuin University. The two organizations set up a Consortium to make experimental studies on IPSec interoperability. This is the first report of the activities and intermediate (the first) results obtained.

Recently, two approaches investigated indexing and retrieving videos. One approach utilized the visual features of individual objects, and the other approach exploited the spatio-temporal relationships between multiple objects. In this paper, we integrate both approaches into a new video model, called the Visual-Spatio-Temporal (VST) model to represent videos. The visual features are modeled in a topological approach and integrated with the spatio-temporal relationships. As a result, we defined rich sets of VST relationships which support and simplify the formulation of more semantical queries. An intuitive query interface which allows users to describe VST features of video objects by sketch and feature specification is presented. The conducted experiments prove the effectiveness of modeling and querying videos by the visual features of individual objects and the VST relationships between multiple objects.

This paper describes a method to normalize the lip position for improving the performance of a visual-information-based speech recognition system. Basically, there are two types of information useful in speech recognition processes; the first one is the speech signal itself and the second one is the visual information from the lips in motion. This paper tries to solve some problems caused by using images from the lips in motion such as the effect produced by the variation of the lip location. The proposed lip location normalization method is based on a search algorithm of the lip position in which the location normalization is integrated into the model training. Experiments of speaker-independent isolated word recognition were carried out on the Tulips1 and M2VTS databases. Experiments showed a recognition rate of 74.5% and an error reduction rate of 35.7% for the ten digits word recognition M2VTS database.

This letter proposes a new detection method of human faces in gray scale image with cluttered background using a face template and elliptical structure of the human face. This proposed method can be applicable even in the cases that the face is much smaller than image size and several faces exist in one image, which is impossible in the existing one.

This paper presents a heuristic graph coloring algorithm named MIPS_CLR, a MInimal-state Processing Search algorithm for the graph CoLoRing problem. Given a graph G(V, E), the goal of this NP-complete problem is to find a color assignment to every vertex in V such that any pair of adjacent vertices must not receive the same color but also the total number of colors should be minimized. The graph coloring problem has been widely studied due to its large number of practical applications in various fields. In MIPS_CLR, a construction stage first generates an initial minimal state composed of as many as colored vertices by a simple greedy algorithm, after a maximal clique of G is found by a maximum clique algorithm. Then, a refinement stage iteratively seeks a solution state while keeping minimality in terms of a cost function by a minimal-state transition method. In this method, the schemes of a best color selection, a random color selection, a color assignment shuffle, and a gradual color expansion are used together to realize the discrete descent search with hill-climbing capabilities. The performance of MIPS_CLR is evaluated through solving DIMACS benchmark graph instances, where the solution quality is generally better than existing algorithms while the computation time is comparable with the best existing one. In particular, MIPS_CLR provides new lower bound solutions for several instances. The simulation results confirm the extensive search capability of our MIPS_CLR approach for the graph coloring problem.

Printed transmission lines have been extensively examined so far, but results obtained there are all concerned with the waveguiding conductors with no loss and zero thickness, except very few results. We have recently studied the transmission characteristics of printed transmission lines in detail, when the waveguiding conductors have finite conductivity and thickness, and we have found an unexpected effect that we call a "mode extinction effect. " This effect results in significant changes in the dispersion behavior of the printed-transmission-line fundamental mode. For a critical thickness, it may turn out that such transmission line can not use in open structural configuration, but must always be used by putting into a packaging box. In this paper, we discuss thoroughly this important effect and related results from the standpoints of both the dispersion behavior and the vector field plots. We also show the measured results of the attenuation constant.

We first reported the simultaneous-propagation effect that the leaky dominant mode can be present on conductor-backed coplanar strips at the same time as the conventional bound dominant mode. We have investigated here numerically and experimentally this effect in detail. Consequently, we have found that it occurs under a certain condition of structural parameters, and also have verified that it affects circuit performance significantly.

In the paper, a theoretical and experimental investigation of a new type of the in-line optical fiber ellipsometer is described. The discussed device, based on the Sagnac interferometer, has the possibility to detect the changes of full polarisation state. The detection of the polarisation state in real time by a system containing standard single-mode fiber and an appropriate applied modulation technique is a new system property. The device uses interferometric measurement technique based on the fourth Fresnel-Arago's condition, which secures very good system accuracy and stability, also presented in the paper.

High-speed and low-power DSPs have been developed for versatile applications, especially for digital communications. These DSPs contain a 16-bit fixed point DSP core with multiple buses, highly tuned instruction set and low-power architecture, featuring 0.45 mA/MIPS, 100-120 MIPS performance by a single CPU core, 200 MIPS performance by dual CPU core architecture, respectively and also contain a 1.2 V low-voltage DSP core with 30 MIPS performance for super low-power applications. In this paper, new architecture VIA2 programming ROM for high-speed and new D flip-flop circuit considering the impact of pocket implantation process for low power are discussed, including key C-MOS process technology.

This paper proposes an ASIP performance optimization method taking clock frequency into account. The performance of an instruction set processor can be measured using the execution time of an application program, which can be determined by the clock cycles to perform the application program divided by the applied clock frequency. Therefore, the clock frequency should also be tuned in order to maximize the performance of the processor under the given design constraints. Experimental results show that the proposed method determines an optimal combination of FUs considering clock frequency.

Although there are many multimedia presentation systems on the market, they have some shortcomings and most of them only can work on one single computer, and few of them can work on Web. Thus, in the thesis we develop a network multimedia presentation system to let users easily design the multimedia presentation without restriction on technology or presentation time and place. Our system includes 3 main components: User Interface that includes temporal specification editor, spatial specification editor and multimedia object interface, Presentation Interface and Knowledge Base. There is a dynamic homepage generator in our system and we propose a displaying algorithm based on the Allen's theory, that there exist 13 temporal relationships between two intervals, for synchronizing the media objects.

A 100MIPS high speed and low power fixed point Digital Signal Processor (DSP) has been developed applying 0.45µm CMOS TLM technology. The DSP contains a 16-bit32K full CMOS static RAM with a hierarchical low power architecture. The device is a RAM based DSP with a total of 4.2 million transistors and a new low power design and process which enabled an approximate 50% reduction in power as compared to conventional DSPs at 40 MHz. In order to cover very wide application requirements, this DSP is capable of operating at 1.0 V for DSP core and 3.3 V for I/O. This was achieved by new level shifter circuitry to interface with cost effective 3 V external commodity products and confirmed 80% of power reduction at Core VDD=2.0 V, I/O VDD=3.3 V at 40MHz. This paper describes the new features of the high speed and low power DSP.

In this paper, a simple frame synchronization system for M-ary Spread Spectrum (M-ary/SS) communication system is analyzed. In particular, synchronization performance, bit error rate performance, and Spread Spectrum Multiple Access (SSMA) performance are analyzed. The frame synchronization system uses the racing counters. The transmitted signal contains framing chips that are added to spreading sequences. In the receiver, the framing chips are detected from several frames. The authors have proposed the simple frame synchronization system that detects framing chips from consecutive 2 frames. In this system, as the number of framing chips increases, synchronization performance improves and bit error rate performance degrades. In this paper a frame synchronization system that improves bit error rate performance is treated and analyzed. As the rusult, when the number of reference frames is 3, the bit error rate is much improved than the conventional system.

In this paper, a simple frame synchronization system for M-ary/SS communication systems is proposed, and synchronization performance and the resulting bit error rate performance are analyzed. The frame synchronization system uses racing counters and framing chips which are added to spreading sequences. M-ary/SS communication systems can improve bit error rate performance under the condition in which there is an additive white gaussian noise. Synchronization of M-ary/SS communication systems is difficult, however, because M-ary/SS communication systems have several spreading sequences. The authors proposed the simple frame synchronization system which uses only one chip in the spreading sequence as a framing signal. This system needs a long time for initial acquisition as the frame length is longer. The proposed system in this paper can make initial acquisition time short by increasing the number of framing chips. The proposed system corresponds to the conventional system when the number of framing chips is l. As the result, it is shown that several framing chips contribute to decrease the initial acquisition time. Moreover, the frame synchronization system can be applied to asynchronous M-ary/SSMA system when different framing chip pattern is assigned to each user.