A simple extension used to assist the decomposition of task-level concurrency within C programs is presented in this paper. The concurrency decomposition is meant to be used as the point of entry for Multiprocessor System-on-Chips (MPSoC) architectures' design-flow. Our methodology allows the (re)use of readily available reference C programs and enables easy and rapid exploration for various alternatives of task partitioning strategies; a crucial task that greatly influences the overall quality of the designed MPSoC. A test case using a JPEG encoder application has been performed and the results are presented in this paper.

This paper describes the IKEv2 protocol and presents how an open-source IKEv2 implementation, in particular OpenIKEv2 has been designed and implemented. All the issues found during this process and how they were solved are also described. Finally, a comparison between existing open-source implementations is presented.

This paper presents a Multiprocessor System-on-Chips (MPSoC) architecture used as an execution platform for the new C-language based MPSoC design framework we are currently developing. The MPSoC architecture is based on an existing SoC platform with a commercial RISC core acting as the host CPU. We extend the existing SoC with a multiprocessor-array block that is used as the main engine to run parallel applications modeled in our design framework. Utilizing several optimizations provided by our compiler, an efficient inter-communication between processing elements with minimum overhead is implemented. A host-interface is designed to integrate the existing RISC core to the multiprocessor-array. The experimental results show that an efficacious integration is achieved, proving that the designed communication module can be used to efficiently incorporate off-the-shelf processors as a processing element for MPSoC architectures designed using our framework.

Exploiting layer7 context is an effective approach to improving the accuracy of detecting malicious messages in network intrusion detection/prevention systems (NIDS/NIPSs). Layer7 context enables us to inspect message formats and the message exchanged order. Unfortunately, layer7-aware NIDS/NIPSs pose crucial implementation issues because they require full TCP and IP reassembly without losing 1) complete prevention, 2) performance, 3) application transparency, or 4) transport transparency. Complete prevention means that the NIDS/NIPS should prevent malicious messages from reaching target applications. Application transparency means not requiring any modifications to and/or reconfiguration of server and client applications. Transport transparency is not to disrupt the end-to-end semantics of TCP/IP. To the best of our knowledge, none of the existing approaches meet all of these requirements. We have developed an efficient mechanism for layer7-aware NIDS/NIPSs that does meet the above requirements. Our store-through does this by forwarding each out-of-order or IP-fragmented packet immediately after copying the packet even if it has not been checked yet by an NIDS/NIPS sensor. Although the forwarded packet might turn out to be a part of an attack message, the store-through mechanism can successfully defend against the attack by blocking one of the subsequent packets that contain another part of attack message. Testing of a prototype in Linux kernel 2.4.30 demonstrated that the overhead of our mechanism is negligible compared with that of a simple IP forwarder even with the presence of out-of-order and IP-fragmented packets. In addition, the experimental results suggest that the CPU and memory usage incurred by our store-through is not significant.

In this study, we propose a simple, yet general and powerful framework for constructing accurate affine invariant regions. In our framework, a method for extracting reliable seed points is first proposed. Then, regions which are invariant to most common affine transformations can be extracted from seed points by two new methods the Path Growing (PG) or the Thresholding Seeded Growing Region (TSGR). After that, an improved ellipse fitting method based on the Direct Least Square Fitting (DLSF) is used to fit the irregularly-shaped contours from the PG or the TSGR to obtain ellipse regions as the final invariant regions. In the experiments, our framework is first evaluated by the criterions of Mikolajczyk's evaluation framework [1], and then by near-duplicate detection problem [2]. Our framework shows its superiorities to the other detectors for different transformed images under Mikolajczyk's evaluation framework and the one with TSGR also gives satisfying results in the application to near-duplicate detection problem.

For fitting an ellipse to a point sequence, ML (maximum likelihood) has been regarded as having the highest accuracy. In this paper, we demonstrate the existence of a "hyperaccurate" method which outperforms ML. This is made possible by error analysis of ML followed by subtraction of high-order bias terms. Since ML nearly achieves the theoretical accuracy bound (the KCR lower bound), the resulting improvement is very small. Nevertheless, our analysis has theoretical significance, illuminating the relationship between ML and the KCR lower bound.

We propose here a composite right/left handed transmission line constructed by using conductor-backed coplanar strips. In this line, we can easily realize a shunt inductor without via because it has the electric-wall symmetry at the guide center. The left-handed nature is verified by both the finite difference time-domain (FDTD) and the equivalent-circuit calculations. Furthermore, we demonstrate the proposed line can easily satisfy the balanced condition for no band gap between the right-handed and the left-handed modes, and can be applied to a leaky-wave antenna, numerically and experimentally.

Large-throughput anomaly prevention mechanism in the upstream side of high-speed (over 10-Gbps) networks is required to prevent various anomalies such as distributed denial of service (DDoS) from causing various network problems. This mechanism requests the processors achieving not only high-speed response for analyzing many packets in a short time but also the flexibility to update the anomaly prevention algorithm. In this research, I assumed a dynamic reconfigurable processor (DRP) was most effective in achieving this anomaly prevention mechanism, for processors used in nodes with the mechanism, and I designed an anomaly prevention mechanism using DRPs. The mechanism can shorten anomaly prevention time in high-speed (10 Gbps) lines using an all-packet analysis. Through a simulation, I achieved the goal of the mechanism achieving a throughput of 83-M packets per second using three DRPs (432 execution elements used). Moreover, with the prototype, it was confirmed that the proposed mechanism prevented anomalies in a short time (constant 0.01 second), which was 3000 times faster than that of a legacy mechanism using a packet sampling method. I also proposed integrated prevention, which was able to reduce the number of execution elements comprising anomaly prevention algorithm against various kinds of anomalies. It was achieved with a simulation that the proposed integrated prevention against three kinds of anomalies (DDoS, worm, and peer to peer (P2P)) reduced the number of execution elements by 24% compared to legacy prevention. In addition, non-stop update was proposed to maintain throughput when updating an anomaly prevention algorithm without packet loss. It was confirmed with a simulation that there was enough time for non-stop update in 10 Gbps 4 lines.

With advent of the ubiquitous network era and due to recent progress of III-V nanotechnology, the present III-V heterostructure microelectronics will turn into what one might call III-V heterostructure nanoelectronics, and may open up a new future in much wider application areas than today, combining information technology, nanotechnology and biotechnology. Instead of the traditional top-down approach, new III-V heterostructure nanoelectronics will be formed on nanostructure networks formed by combination of top-down and bottom-up approaches. In addition to communication devices, emerging devices include high speed digital LSIs, various sensors, various smart-chips, quantum LSIs and quantum computation devices covering varieties of application areas. Ultra-low power quantum LSIs may become brains of smart chips and other nano-space systems. Achievements of new functions and higher performances and their on chip integration are key issues. Key processing issue remains to be understanding and control of nanostructure surfaces and interfaces in atomic scale.

A wireless interface for stacked chips in System-in-a-Package is presented. The interface utilizes inductive coupling between metal inductors. S21 parameters of the inductive coupling are measured between chips stacked in face-up for the first time. Calculations from a theoretical model have good agreement with the measurements. A transceiver circuit for Non-Return-to-Zero signaling is developed to reduce power dissipation. The transceiver is implemented in a test chip fabricated in 0.35 µm CMOS and the chips are stacked in face-up. The chips communicate through the transceiver at 1.2 Gb/s/ch with 46 mW power dissipation at 3.3 V over 300 µm distance. A scaling scenario is derived based on the theoretical model and measurement results. It indicates that, if the communication distance is reduced to 13 µm in 70 nm CMOS, 34 Tbps/mm2 will be obtained.

This paper presents a new conic section extraction approach that can extract all conic sections (lines, circles, ellipses, parabolas and hyperbolas) simultaneously. This approach is faster than the conventional approaches with a computational complexity that is O(n), where n is the number of edge pixels, and is robust in the presence of moderate levels of noise. It has been combined with a classification tree to produce an offline character recognition system that is invariant to scale, rotation, and translation. The system was tested with synthetic images and with images scanned from real world sources with good results.

In this letter, we provide a solution to the stabilization problem of a class of Lipschitz nonlinear systems by output feedback. Via the newly proposed nonlinearity characterization function (NCF) concept, we propose an effective method in designing an output feedback controller. Under the suggested sufficient condition which is derived by using the NCF, the proposed control scheme achieves the global exponential stabilization.

We have determined the thickness and optical constants (refractive index and extinction coefficient) of each layer in the multi-layer organic light emitting diode (OLED) devices based on phosphorescent platinum octaethyl porphine (PtOEP) using a phase modulated spectroscopic ellipsometer. The thickness of each layer estimated from the ellipsometric measurement is different from the thickness measured with quartz oscillator during the evaporation of organic materials. The deviation of total multi-layer thickness is about 5%, while the deviation in each of N, N'-bis(1-naphtyl)-N, N'-diphenyl-1,1'-biphenyl-4,4'-diamine (α-NPD) and aluminum tris 8-hydroxyquinoline (Alq3) layers is about 20-25%. Additionally the spectra of refractive index and extinction coefficient of Alq3 and α-NPD layers are different from those that are measured using the single layer films. These results are understood by penetration of organic material from the neighboring layers in the multi-layer structure devices.

Liquid-crystal devices with in-plane switching electrodes (IPS-LCD) are superior to twisted nematic ones in their wider range of viewing angle, but show serious color shift with viewing angle. The color shift is a phenomenon governed by the three-dimensional orientation of liquid-crystal molecules. In order to evaluate such effects numerically, light wave propagation in the IPS-LCD is studied using a two-dimensional finite-difference time-domain method, where all six components of electromagnetic field are analysed and the three-dimensional properties of liquid-crystal materials are taken into account through the dielectric tensor. The computational space termination is provided by a combination of the uniaxial perfectly matched layer and periodic boundary conditions. It is found for the first time numerically that the color shift effects strongly depend on the asymmetrical profile of liquid-crystal orientation, which is originated from the small pretilt angle.

We present a novel mesh representation scheme exploiting the characteristics of triangle strips, called progressives strips, which gives rendering-efficient triangulation data at the rendering stage in a graphics system such as progressive transmission where the mesh topology changes continuously. Progressive strips consist of a set of triangle strips simplified to the base mesh and a set of refinement steps required to recover incrementally the original mesh at full resolution. We also propose an improved triangle strip filtering algorithm and the encoding of strip-edge collapses in order to reduce efficiently the redundant triangles and the amount of refinement information, both of which may increase as the mesh degrades. Our approach increases the overall graphics performance by reducing the amount of data sent to the graphics pipeline.

A hybrid method-of-moments (MoM) and immittance approach for efficient and accurate analysis of printed slots and strips of arbitrary shape in layered waveguide for various applications has been proposed. An impedance-type MoM is formulated from the electric field integral equation (EFIE) for printed strip case and an admittance-type MoM is formulated from the magnetic field integral equation (MFIE) for the printed slot case, using the Galerkin's technique. Immittance approach has been used to calculate spectral dyadic Green's functions for the layered waveguide. For efficient analysis of large and complex structures, equivalent circuit parameters of a block are first extracted and complete structure is analyzed through cascaded ABCD matrices. The equivalent circuit characterization of printed strip and slot in layered waveguide has been done for the first time. Finite periodic structure loaded with printed strips has been investigated and it shows the electromagnetic bandgap (EBG) behavior. The electromagnetic (EM) program hence developed is checked for its numerical accuracy and efficiency with results generated with High-frequency structure simulator (HFSS) and shows good performance.

A new high-speed and low-power digital signal processor (DSP) core, C55x, was developed for next generation applications such as 3G cellular phone, PDA, digital still camera (DSC), audio, video, embedded modem, DVD, and so on. To support such MIPS-rich applications, a packet size of an instruction fetch increased from 16-bit to 32-bit comparing with the world's most popular C54x DSP core, while maintaining complete software compatibility with the legacy DSP code. An on-chip instruction buffer queue (IBQ) automatically unpacks the packets and issues multiple instructions in parallel for the efficient use of circuit resources. The efficiency of the parallelism has been further improved by additional hardwares such as second 1717-bit MAC, a 16-bit ALU, and three temporary registers that can be used for simple computations. Four 40-bit accumulators make it possible to execute more operation per cycle with dramatically reduced overall power consumption. These new architecture allows two times efficiency of instruction per cycle (IPC) than the previous DSP core on typical applications at the same MHz. The new DSP core was designed for TI's two 130 nm technologies, one with high-VT for low-leakage and middle-performance operation at 1.5 V, and the other with low-VT for high-performance and low-VDD operation at 1.2 V, to provide best choices for any applications with a single layout data base. With the low-leakage process, the DSP core operates at over 200 MHz with 188 µA/MHz (at 75% Dual MAC + 25% ADD) active power and less than 1.63 µA standby current. The high-performance process provides it with 300 MHz with 169 µA/MHz active power and less than 680 µA standby current. The new core was designed by a semi-custom approach (ASIC + custom library) using 5-level Cu metal system with low-k dielectric material of fluorosilicate glass (FSG), and about one million transistors are contained in the core. The total balance of its power, performance, area, and leakage current (PPAL) is well suitable to most of next generation applications. In this paper, we will discuss features of the new DSP core, including circuit design techniques for high-speed and low-power, and present an example product.

Software reuse has been recognized as important. According to our research, when a software product is reused, products correlated to the reused one may be reusable. This paper proposes a model for software products and a technique to retrieve correlated products. The paper also presents equations to evaluate correlation values, which is guidance for selecting reusable correlated products. Since correlated products can be identified by tracing product relationships, the proposed model manages both products and relationships.

Automatic image inspector inspects the quality of printed circuit boards using image-processing technology. In this study, we change an automatic inspection problem into a problem for detecting the signal singularities. Based on the wavelet theory that the wavelet transform can focus on localized signal structures with a zooming procedure, a novel singularity detection and measurement algorithm is proposed. Singularity positions are detected with the local wavelet transform modulus maximum (WTMM) line, and the Lipschitz exponent is estimated at each singularity from the decay of the wavelet transform amplitude along the WTMM line. According to the theoretical analysis and computer simulation results, the proposed algorithm is shown to be successful for solving the automatic inspection problem and calculating the Lipschitz exponents of signals. These Lipschitz exponents successfully characterize singular behavior of signals at singularities.

The current paper presents an effective deblocking algorithm for block-based coded images using singularity detection in a wavelet transform. Blocking artifacts appear periodically at block boundaries in block-based coded images. The local maxima of a wavelet transform modulus detect all singularities, including blocking artifacts, from multiscale edges. Accordingly, the current study discriminates between a blocking artifact and an edge by estimating the Lipschitz regularity of the local maxima and removing the wavelet transform modulus of a blocking artifact that has a negative Lipschitz regularity exponent. Experimental results showed that the performance of the proposed algorithm was objectively and subjectively superior.