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[Keyword] PDE(6hit)

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  • The Evaluation of the Interface Properties of PdEr-Silicide on Si(100) Formed with TiN Encapsulating Layer and Dopant Segregation Process

    Rengie Mark D. MAILIG  Min Gee KIM  Shun-ichiro OHMI  

     
    PAPER-Electronic Materials

      Vol:
    E103-C No:6
      Page(s):
    286-292

    In this paper, the effects of the TiN encapsulating layer and the dopant segregation process on the interface properties and the Schottky barrier height reduction of PdEr-silicide/n-Si(100) were investigated. The results show that controlling the initial location of the boron dopants by adding the TiN encapsulating layer lowered the Schottky barrier height (SBH) for hole to 0.20 eV. Furthermore, the density of interface states (Dit) on the order of 1011eV-1cm-2 was obtained indicating that the dopant segregation process with TiN encapsulating layer effectively annihilated the interface states.

  • PdEr-Silicide Formation and Contact Resistivity Reduction to n-Si(100) Realized by Dopant Segregation Process

    Shun-ichiro OHMI  Yuya TSUKAMOTO  Weiguang ZUO  Yasushi MASAHIRO  

     
    PAPER

      Vol:
    E101-C No:5
      Page(s):
    311-316

    In this paper, we have investigated the PdEr-silicide formation utilizing a developed PdEr-alloy target for sputtering, and evaluated the contact resistivity of PdEr-silicide layer formed on n-Si(100) by dopant segregation process for the first time. Pd2Si and ErSi2 have same hexagonal structure, while the Schottky barrier height for electron (Φbn) is different as 0.75 eV and 0.28 eV, respectively. A 20 nm-thick PdEr-alloy layer was deposited on the n-Si(100) substrates utilizing a developed PdEr-alloy target by the RF magnetron sputtering at room temperature. Then, 10 nm-thick TiN encapsulating layer was in-situ deposited at room temperature. Next, silicidation was carried out by the RTA at 500 for 5 min in N2/4.9%H2 followed by the selective etching. From the J-V characteristics of fabricated Schottky diode, qΦbn was reduced from 0.75 eV of Pd2Si to 0.43 eV of PdEr-silicide. Furthermore, 4.0x10-8Ωcm2 was extracted for the PdEr-silicide to n-Si(100) by the dopant segregation process.

  • Post-Silicon Clock-Timing Tuning Based on Statistical Estimation

    Yuko HASHIZUME  Yasuhiro TAKASHIMA  Yuichi NAKAMURA  

     
    PAPER

      Vol:
    E91-A No:9
      Page(s):
    2322-2327

    In deep-submicron technologies, process variations can significantly affect the performance and yield of VLSI chips. As a countermeasure to the variations, post-silicon tuning has been proposed. Deskew, where the clock timing of flip-flops (FFs) is tuned by inserted programmable delay elements (PDEs) into the clock tree, is classified into this method. We propose a novel deskew method that decides the delay values of the elements by measuring a small amount of FFs' clock timing and presuming the rest of FFs' clock timings based on a statistical model. In addition, our proposed method can determine the discrete PDE delay value because the rewriting constraint satisfies the condition of total unimodularity.

  • Progressive Transform-Based Phase Unwrapping Utilizing a Recursive Structure

    Andriyan Bayu SUKSMONO  Akira HIROSE  

     
    PAPER-Sensing

      Vol:
    E89-B No:3
      Page(s):
    929-936

    We propose a progressive transform-based phase unwrapping (PU) technique that employs a recursive structure. Each stage, which is identical with others in the construction, performs PU by FFT method that yields a solution and a residual phase error as well. The residual phase error is then reprocessed by the following stages. This scheme effectively improves the gradient estimate of the noisy wrapped phase image, which is unrecoverable by conventional global PU methods. Additionally, by incorporating computational strength of the transform PU method in a recursive system, we can realize a progressive PU system for prospective near real-time topographic-mapping radar and near real-time medical imaging system (such as MRI thermometry and MRI flow imager). PU performance of the proposed system and the conventional PU methods are evaluated by comparing their residual error quantitatively with a fringe-density-related error metric called FZX (fringe's zero-crossing) number. Experimental results for simulated and real InSAR phase images show significant, progressive improvement over conventional ones of a single-stage system, which demonstrates the high applicability of the proposed method.

  • Scale-Space Processing of Point-Sampled Geometry for Efficient 3D Object Segmentation

    Hamid LAGA  Hiroki TAKAHASHI  Masayuki NAKAJIMA  

     
    PAPER

      Vol:
    E88-D No:5
      Page(s):
    963-970

    In this paper, we present a novel framework for analyzing and segmenting point-sampled 3D objects. Our algorithm computes a decomposition of a given point set surface into meaningful components, which are delimited by line features and deep concavities. Central to our method is the extension of the scale-space theory to the three-dimensional space to allow feature analysis and classification at different scales. Then, a new surface classifier is computed and used in an anisotropic diffusion process via partial differential equations (PDEs). The algorithm avoids the misclassifications due to fuzzy and incomplete line features. Our algorithm operates directly on points requiring no vertex connectivity information. We demonstrate and discuss its performance on a collection of point sampled 3D objects including CAD and natural models. Applications include 3D shape matching and retrieval, surface reconstruction and feature preserving simplification.

  • Implementation of the Multicolored SOR Method on a Vector Supercomputer

    Seiji FUJINO  Ryutaro HIMENO  Akira KOJIMA  Kazuo TERADA  

     
    PAPER

      Vol:
    E80-D No:4
      Page(s):
    518-523

    We describe the implementation of an iterative method with the goal of gaining a long vector length. The strategy for vectorization by means of multipoint stencils used for discretization of the partial differential equations is discussed. Numerical experiments show that the strategy that requires certain restrictions on the number of grid points in the x and y directions improves the performance on the vector supercomputer.