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[Keyword] TCI(5hit)

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  • Analysis and Evaluation of Electromagnetic Interference between ThruChip Interface and LC-VCO

    Junichiro KADOMOTO  So HASEGAWA  Yusuke KIUCHI  Atsutake KOSUGE  Tadahiro KURODA  

     
    BRIEF PAPER

      Vol:
    E99-C No:6
      Page(s):
    659-662

    This paper presents analysis and simple design guideline for ThruChip Interface (TCI) as located by LC-VCO which is used in high-speed SoC. The electromagnetic interference (EMI) from TCI channels to LC-VCO is analyzed and evaluated. The accuracy of the analysis and design guidelines is verified through the test-chip verification.

  • A Study of Physical Design Guidelines in ThruChip Inductive Coupling Channel

    Li-Chung HSU  Junichiro KADOMOTO  So HASEGAWA  Atsutake KOSUGE  Yasuhiro TAKE  Tadahiro KURODA  

     
    PAPER-Physical Level Design

      Vol:
    E98-A No:12
      Page(s):
    2584-2591

    ThruChip interface (TCI) is an emerging wireless interface in three-dimensional (3-D) integrated circuit (IC) technology. However, the TCI physical design guidelines remain unclear. In this paper, a ThruChip test chip is designed and fabricated for design guidelines exploration. Three inductive coupling interface physical design scenarios, baseline, power mesh, and dummy metal fill, are deployed in the test chip. In the baseline scenario, the test chip measurement results show that thinning chip or enlarging coil dimension can further reduce TCI power. The power mesh scenario shows that the eddy current on power mesh can dramatically reduce magnetic pulse signal and thus possibly cause TCI to fail. A power mesh splitting method is proposed to effectively suppress eddy current impact while minimizing power mesh structure impact. The simulation results show that the proposed method can recover 77% coupling coefficient loss while only introducing additional 0.5% IR-drop. In dummy metal fill case, dummy metal fill enclosed within TCI coils have no impact on TCI transmission and thus are ignorable.

  • Relay Transmission Thruchip Interface with Low-Skew 3D Clock Distribution Network

    Yasuhiro TAKE  Tadahiro KURODA  

     
    PAPER

      Vol:
    E98-C No:4
      Page(s):
    322-332

    This paper presents an inductive coupling interface using a relay transmission scheme and a low-skew 3D clock distribution network synchronized with an external reference clock source for 3D chip stacking. A relayed transmission scheme using one coil is proposed to reduce the number of coils in a data link. Coupled resonation is utilized for clock and data recovery (CDR) for the first time in the world, resulting in the elimination of a source-synchronous clock link. As a result, the total number of coils required is reduced to one-fifth of the conventional number required, yielding a significant improvement in data rate, layout area, and energy consumption. A low-skew 3D clock distribution network utilizes vertically coupled LC oscillators and horizontally coupled ring oscillators. The proposed frequency-locking and phase-pulling scheme widens the lock range to $pm$ 10%. Two test chips were designed and fabricated in 0.18 $mu$m CMOS. The bandwidth of the proposed interface using relay transmission ThruChip Interface (TCI) is 2.7 Gb/s/mm$^2$; energy consumption per chip is 0.9 pJ/b/chip. Clock skew is less than 18- and 25- ps under a 1.8- and 0.9- V supply. The distributed RMS jitter is smaller than 1.72 ps.

  • Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration

    Li-Chung HSU  Masato MOTOMURA  Yasuhiro TAKE  Tadahiro KURODA  

     
    PAPER

      Vol:
    E98-C No:4
      Page(s):
    288-297

    This paper presents work on integrating wireless 3-D interconnection interface, namely ThruChip Interface (TCI), in three-dimensional field-programmable gate array (3-D FPGA) exploration tool (TPR). TCI is an emerging 3-D IC integration solution because of its advantages over cost, flexibility, reliability, comparable performance, and energy dissipation in comparison to through-silicon-via (TSV). Since the communication bandwidth of TCI is much higher than FPGA internal logic signals, in order to fully utilize its bandwidth, the time-division multiplexing (TDM) scheme is adopted. The experimental results show 25% on average and 58% at maximum path delay reduction over 2-D FPGA when five layers are used in TCI based 3-D FPGA architecture. Although the performance of TCI based 3-D FPGA architecture is 8% below that of TSV based 3-D FPGA on average, TCI based architecture can reduce active area consumed by vertical communication channels by 42% on average in comparison to TSV based architecture and hence leads to better delay and area product.

  • Multiple Document Summarization System GOLD

    Tatsumi YOSHIDA  Shigeru MASUYAMA  

     
    PAPER

      Vol:
    E86-D No:9
      Page(s):
    1719-1727

    We developed a multiple document summarization system GOLD. This system generates a single summary from relevant newspaper articles with any summarization rate specified by a user. GOLD is incorporated a number of methods to summarize. In particular, some methods for sentence reduction are useful to shorten each sentence. As a result, it increased the number of outputted sentences which include important information. We participated in task B of NTCIR3 TSC2 to evaluate this system. GOLD exhibits a good performance in content-based evaluation which suggests that summarization methods employed by GOLD are promising for practical use.