Low-density parity-check (LDPC) codes can be used to improve the storage reliability of multi-level cell (MLC) flash memories because of their strong error-correcting capability. In order to improve the weighted bit-flipping (WBF) decoding of LDPC codes in MLC flash memories with cell-to-cell interference (CCI), we propose two strategies of normalizing weights and adjusting log-likelihood ratio (LLR) values. Simulation results show that the WBF decoding under the proposed strategies is much advantageous in both error and convergence performances over existing WBF decoding algorithms. Based on complexity analysis, the strategies provide the WBF decoding with a good tradeoff between performance and complexity.

In this paper, a weighted multiple bit flipping (WMBF) algorithman for decoding low-density parity-check (LDPC) codes is proposed first. Then the improved WMBF algorithm which we call the efficient weighted bit-flipping (EWBF) algorithm is developed. The EWBF algorithm can dynamically choose either multiple bit-flipping or single bit-flipping in each iteration according to the log-likelihood ratio of the error probability of the received bits. Thus, it can efficiently increase the convergence speed of decoding and prevent the decoding process from falling into loop traps. Compared with the parallel weighted bit-flipping (PWBF) algorithm, the EWBF algorithm can achieve significantly lower computational complexity without performance degradation when the Euclidean geometry (EG)-LDPC codes are decoded. Furthermore, the flipping criterion does not require any parameter adjustment.

We present a simple decoding algorithm that modifies soft bit-flipping algorithm for decoding LDPC codes. In our method, a new parameter is explored to distinguish the variables (symbols) belonging to the same number of unsatisfied constraints. A token is also assigned in the method to avoid repeated flipping of the same variable, rather than using a constant taboo length. Our scheme shows a similar computational load as the taboo-based algorithm, while having a similar decoding performance as the belief propagation algorithm.

This paper presents a new deterministic built-in test scheme using a neighborhood pattern generator (NPG) to guarantee complete fault efficiency with small test-data storage. The NPG as a decoding logic generates both a parent pattern and deterministic child patterns within a small Hamming distance from the parent pattern. A set of test cubes is encoded as a set of seeds for the NPG. The proposed method is practically acceptable because no impact on a circuit under test is required and the design of the NPG does not require the results of test generation. We also describe an efficient seed generation method for the NPG. Experimental results for benchmark circuits demonstrate that the proposed method can significantly reduce the storage requirements when compared with other deterministic built-in test methods.