The present paper proposes differential transmission line structures on Si ULSI. Interconnect structures are examined using numerical results from a two-dimensional electromagnetic simulation (Ansoft, 2D Extractor). The co-planar and diagonal-pair lines are found to have superior characteristics for gigahertz signal propagation through long interconnects. The proposed diagonal-pair line can reduce the crosstalk noise and interconnect resource concurrently.

In the present GHz-clock high-density LSI, a design of signal lines is getting so critical that the transmission line analysis should be introduced to signal line design. This leads to the complex design of line structure and i/o drivers including impedance matching. Our target is to implement a system-in-package (SiP) for software-defined-radio (SDR). The SiP operates up to 10 GHz, and requires a compact and high-density packaging technology with a simple signal wiring design. In this paper, we propose a new concept of 3-D multilayer-stacked SiP. The new 3-D packaging concept includes (1) design guideline for interconnection lengths, (2) bridging register circuits in LSI chips, (3) flip-chip microbump bonding technology of chips onto system-buildup printed wiring boards (PWB), (4) multilayer-stacked 3-D package of several sets of chips and PWB, and (5) 100-µm-diameter bumps at peripheral region of PWB as vertical via-bump bus lines. A critical interconnect length, in which interconnect wiring is treated as a conventional RC line, is discussed for wiring design. Both wiring lengths in LSI chips and that among chips corresponding to total thickness of vertical bus lines are designed to be shorter than the critical length. The key points of the 3-D package for GHz signal transfer are a delay guarantee due to limitation of line length and separation between local lines in a chip and a bus line among chips.

Three dimensional (3-D) optics offers potential advantages to the massively-parallel systems over electronics from the view point of information transfer. The purpose of this paper is to survey some aspects of the 3-D optical interconnection technology for the future massively-parallel computing systems. At first, the state-of-art of the current optoelectronic array devices to build the interconnection networks are described, with emphasis on those based on the semiconductor technology. Next, the principles, basic architectures, several examples of the 3-D optical interconnection systems in neural networks and multiprocessor systems are described. Finally, the issues that are needed to be solved for putting such technology into practical use are summarized.

This paper was written for LSI engineers in order to demonstrate the effect of optical interconnections in LSIs to improve both the speed and power performances of 0.5 and 0.2 µm CMOS microprocessors. The feasibilities and problems regarding new micronsize optoelectronic devices as well as associated electronics are discussed. Actual circuit structures clocks and bus lines used for optical interconnection are discussed. Newly designed optical interconnections and the speed power performances are compared with those of the original electrical interconnection systems.