To improve throughput of Electron Beam Direct Writing (EBDW) with Character Projection (CP) method, a structured routing architecture (SRA) has been proposed to restrict VIA placement and wire-track transition. It reduces possible layout patterns in the interconnect layers, and increases VIA and metal figure numbers in the EB shots while suppressing the CP character number explosion. In this paper, we discuss details of the SRA design methodology, and demonstrate the CP performance by SRA in comparison with other EBDW techniques. Our experimental results show viable CP performance for practical use, and prove SRA's feasibility in 14nm mass fabrication.

Character projection (CP) is a high-speed mask-less exposure technique for electron-beam direct writing (EBDW). In CP exposure of VIA layers, higher throughput is realized if more VIAs are exposed in each EB shot, but it will result in huge number of VIA characters to cover arbitrary VIA arrangements. We adopt one-dimensional VIA arrays as the basic CP character architecture to increase VIA numbers in an EB shot while saving the stencil area by superposed character arrangement. In addition, CP throughput is further improved by layout constraints on the VIA placement in the detail routing phase. Our experimental results proved the feasibility of our exposure strategy in the practical CP use in 14nm lithography.

We propose a character size optimization technique to reduce the number of EB shots of multi-column-cell (MCC) lithographic systems in which transistor patterns are projected with multiple column cells in parallel. Each and every column cell is capable of projecting patterns with character projection (CP) and variable shaped beam (VSB) methods. Seeking the optimal character size of characters contributes to minimizing the number of EB shots and reducing the fabrication cost for ICs. Experimental results show that the character size optimization achieved 70.6% less EB shots in the best case with an available electron beam (EB) size. Our technique also achieved 40.6% less EB shots in the best case than a conventional character sizing technique.

Character projection (CP) lithography is utilized for maskless lithography and is a potential for the future photomask manufacture because it can project ICs much faster than point beam projection or variable-shaped beam (VSB) projection. In this paper, we first present a projection mask set development methodology for multi-column-cell (MCC) systems, in which column-cells can project patterns in parallel with the CP and VSB lithographies. Next, we present an INLP (integer nonlinear programming) model as well as an ILP (integer linear programming) model for optimizing a CP mask set of an MCC projection system so that projection time is reduced. The experimental results show that our optimization has achieved 33.4% less projection time in the best case than a naive CP mask development approach. The experimental results indicate that our CP mask set optimization method has virtually increased cell pattern objects on CP masks and has decreased VSB projection so that it has achieved higher projection throughput than just parallelizing two column-cells with conventional CP masks.

The character projection (CP) lithography is utilized for maskless lithography and is a potential for the future photomask fabrication. The drawback of the CP lithography is its low throughput and leads to a price rise of IC devices. This paper discusses a technology mapping technique for enhancing the throughput of the CP lithography. The number of electron beam (EB) shots to project an entire chip directly determines the fabrication time for the chip as well as the throughput of CP equipment. Our technology mapping technique maps EB shot count-effective cells to a circuit in order to increase the throughput of CP equipment. Our technique treats the number of EB shots as an objective to minimize. Comparing with a conventional technology mapping, our technology mapping technique has achieved 26.6% reduction of the number of EB shots for the front-end-of-the-line (FEOL) process without any performance degradation of ICs. Moreover, our technology mapping technique has achieved a 54.6% less number of EB shots under no performance constraints. It is easy for both IC designers and equipment developers to adopt our technique because our technique is a software approach with no additional modification on CP equipment.

We propose a shot reduction technique of character projection (CP) Electron Beam Direct Writing (EBDW) using combined cell stencil (CCS) or the advanced process technology. CP EBDW is expected both to reduce mask costs and to realize quick turn around time. One of major issue of the conventional CP EBDW, however, is a throughput of lithography. The throughput is determined by numbers of shots, which are proportional to numbers of cell instances in LSIs. The conventional shot reduction techniques focus on optimization of cell stencil extraction, without any modifications on designed LSI mask patterns. The proposed technique employs the proposed combined cell stencil, with proposed modified design flow, for further shot reduction. We demonstrate 22.4% shot reduction within 4.3% area increase for a microprocessor and 28.6% shot reduction for IWLS benchmarks compared with the conventional technique.

We propose a cell library development methodology for throughput enhancement of character projection equipment. First, an ILP (Integer Linear Programming)-based cell selection is proposed for the equipment for which both of the CP (Character Projection) and VSB (Variable Shaped Beam) methods are available, in order to minimize the number of electron beam (EB) shots, that is, time to fabricate chips. Secondly, the influence of cell directions on area and delay time of chips is examined. The examination helps to reduce the number of EB shots with a little deterioration of area and delay time because unnecessary directions of cells can be removed. Finally, a case study is shown in which the numbers of EB shots are shown for several cases.