With the advent of the Internet of Things (IoT), short packet transmissions will dominate the future wireless communication. However, traditional coherent demodulation and channel estimation schemes require large pilot overhead, which may be highly inefficient for short packets in multipath fading scenarios. This paper proposes a novel pilot-free short packet structure based on the association of modulation on conjugate-reciprocal zeros (MOCZ) and tail-biting convolutional codes (TBCC), where a noncoherent demodulation and decoding scheme is designed without the channel state information (CSI) at the transceivers. We provide a construction method of constellation sets and demodulation rule for M-ary MOCZ. By deriving low complexity log-likelihood ratios (LLR) for M-ary MOCZ, we offer a reasonable balance between energy and bandwidth efficiency for joint coding and modulation scheme. Simulation results show that our proposed scheme can attain significant performance and throughput gains compared to the pilot-based coherent modulation scheme over multipath fading channels.

This letter describes an efficient architecture for a Software Defined Radio (SDR) Wideband Code Division Multiple Access (WCDMA) receiver using for high performance wireless communication systems. The architecture is composed of a Radio Frequency (RF) front-end, an Analog-to-Digital Converter (ADC), and a Quadrature Amplitude Modulation (QAM) demodulator. A coherent demodulator, with a complete digital synchronization scheme, achieves the bit-error rate (BER) of 10-6 with the implementation loss of 0.5 dB for a raw Quadrature Phase Shift King (QPSK) signal.

PSK coherent demodulation has difficulty in achieving high speed carrier extraction and symbol synchronization when implementing to slow FH-SS radio system. On the other hand, implementation to FPGA has the requirement of a small gate size to design because of FPGA cost issue. We developed a QPSK coherent demodulation digital modem for FH-SS radio systems using FPGA by solving problems. The designed modem performs symbol synchronization with no carrier extractions, under the limitation of the small gate size requirement. The modem employs shift arithmetic operation and a comb digital BPF to achieve very good synchronization lock-up performance with small gate size. In this paper, the symbol synchronization and the carrier tracking scheme are mainly discussed. Analysis of its performance and stability are also explained. The achievement of its very good performance is presented by experimental measurement.