The researches on model-based testing mainly focus on the models with single component, such as FSM and EFSM. For the network protocols which have multiple components communicating with messages, CFSM is a widely accepted solution. But in some network protocols, parallel and data-shared components maybe exist in the same network entity. It is infeasible to precisely specify such protocol by existing models. In this paper we present a new model, Parallel Parameterized Extended Finite State Machine (PaP-EFSM). A protocol system can be modeled with a group of PaP-EFSMs. The PaP-EFSMs work in parallel and they can read external variables form each other. We present a 2-stage test generation approach for our new models. Firstly, we generate test sequences for internal variables of each machine. They may be non-executable due to external variables. Secondly, we process the external variables. We make the sequences for internal variables executable and generate more test sequences for external variables. For validation, we apply this method to the conformance testing of real-life protocols. The devices from different vendors are tested and implementation faults are exposed.

This paper proposes a framework for modular verification of evolving component-based software. This framework includes two stages: modular conformance testing for updating inaccurate models of the evolved components and modular verification for evolving component-based software. When a component is evolved after adapting some refinements, the proposed framework focuses on this component and its model in order to update the model and recheck the whole evolved system. The framework also reuses the previous verification results and the previous models of the evolved components to reduce the number of steps required in the model update and modular verification processes. An implementation and some experimental results are presented.

A new technique is proposed to generate the executable and synchronizable (i. e. , e-synchronizable) test sequence for the protocol implementation to be conformable to its data portion specification. The protocol's control portion is specified as a finite state machine (FSM), and its data portion is specified as a set of rules. The technique involves converting the FSM and the rules into the DuplexSelect digraph, from which we can generate test sequences which are both synchronizable (i. e. , encounter no synchronization problems) and executable (i. e. , associated with parameter values which do not violate the rules). The Selecting Chinese Postman Algorithm is then used for minimizing the cost of the e-synchronizable test sequence that verifies each rule at least once.

This paper discusses a design and an implementation of a MIB tester, a conformance test tool of Management Information Base (MIB) for TMN. A remote test method is used as a practical test configuration. We classify test purposes into three; basic interconnection test, capability test and behaviour test. Test items for the capability test are defined according to Managed Object Conformance Statement (MOCS) and Managed Relationship Conformance Statement (MRCS). Test items for the behaviour test is defined according to GDMO BEHAVIOUR clause. The MIB tester automatically generates test scenarios for capability tests, which are also used as those for the basic interconnection test, and supports the scenario creation of the behaviour test in an user-friendly manner. We evaluate the implemented MIB tester through its application to the actual TMN agents.

This paper studies the problem of testing concurrent systems considered as blackboxes and specified using asynchronous Communicating Finite State Machines. We present an approach to derive test cases for concurrent systems in a succinct and formal way. The approach addresses the state space explosion problem by introducing a causality relation model and the concept of logical time to express true concurrency and describe timing constraints on events. The conformance relation between test cases and trace observed from the real system is defined, and a new test architecture as well as a test case application is presented according to the conformance relation defined. To improve verdict capability of test cases, the approach is enhanced by relaxing the unit-time assumption to any natural number. And a computationally efficient algorithm for the enhanced approach is presented and the algorithm is evaluated in terms of computational efficiency and verdict capability. Finally the approach is generalized to describe timing constraints by any real numbers.

A Unique Input/Output (UIO) sequence for the state J of a protocol is a sequence of input/output pairs that is unique to state J. Obtaining UIO sequences from the protocol specification is a very important problem in protocol conformance testing. Let n and m be the total number of states and transitions of the protocol, respectively, and dmax be the largest outdegree of any state, W. Chun and P. D. Amer proposed an O(n2(dmax)2n-1) algorithm to obtain the minimum-length UIO sequences (where the length refers to the number of input/output pairs). However, n and m are normally very large for real protocols. In this paper, we propose an O(n*m) algorithm for obtaining UIO sequences. In theory, our algorithm yields a UIO sequence which contains at most n1 input/output pairs. In experimentation, ten protocol examples collected from recent papers, the ISO TP0 protocol, the ISDN Q. 931 network-side protocol, and the CCITT X. 25 protocol show that in average the obtained UIO sequences are only 11.8% longer than the minimum-length ones, and 97.4% of the existent UIO sequences can be found. And our algorithm is extended for minimizing the cost of UIO sequences and for obtaining synchronizable UIO sequences, which have not been achieved by any algorithm proposed earlier.

Conformance testing is to see if the protocol implementation conforms to its specification. A lot of test sequences have been developed for testing centers. Yet directly applying these test sequences to the simple testing system in laboratories suffers from the frequently-occurred synchronization problems. This paper proposes a new technique to disconnect a test sequence into segments based on their functions, and reconnects them into a new test sequence that simulates these functions yet suffers less from the synchronization problems.

This paper presents testing methods for a logic synthesis system which supports the standard HDL UDL/I, focusing on conformance test to the language specification. Conformance test, to prove that the system completely satisfies the language specification, is very important to provide a unified design environment for users of CAD tools which support the language. The basic idea of our testing methods is using a logic simulator, due to a limited schedule for the test execution. We classified the test into two: unit test and integration test. Unit test is a test of each individual functionality of the system, and integration test is a test to prove that the whole system works correctly and satisfies the language specification. And we prepared and used various kinds of test data. One of them is the UDL/I Test Suite and it was also utilized to observe progress of language coverage by the system during the test execution.

Conformance testing techniques are required for the efficient production of reliable communication protocols. A lot of conformance testing techniques have been developed. However, most of them can only decide whether an implemented protocol conforms to its specification. That is, the exact locations of faults are not determined by them. This paper presents some conditions that enable to find locations of multiple faults, and then proposes a test sequence generation technique under such conditions. The correctness proof and complexity analysis of the proposed technique are also given. The characteristics of this technique are to generate test sequences based on protocol specifications and interim test results, and to find locations of multiple faults in protocol implementations. Although the length of the test sequence generated by the proposed technique is a little longer than the one generated by the previous one, the class to which the proposed technique can be applied is larger than that to which the previous one can be applied.

There is a wide perception of the need for conformance and interoperability testing to ensure the interoperability of open systems. In the circumstances, we have been making efforts to establish a system for interconnectability testing, which is a type of the interoperability testing. In this paper, we discuss an interconnectability testing system, named AICTS (AIC's InterConnectability Testing System) that we have designed. We also discuss a conformance testing system, named ACTS (AIC Conformance Test System), which we developed as the first step toward building an interconnectability testing system. ACTS is capable of extensions for an interconnectability testing system.

As to the method of multi-layer testing, up to now, the testing system (called PROVES) which testes effectively each N-layer protocol implement of SUT (System Under Test) using the functions of derail-points located between N-layer and (N+1)-layer protocol implements in a test system has been proposed. The test logic programs, which are embedded in the derail-points of the test system, play an important role to realize the protocol error test sequences in the test system. Namely, they modify, add, or delete the correct protocol commands/responses output from the protocol implement part of the lest system, sends these erroneous commands/responses to SUT and observes the output from SUT. This paper proposes the method of validating the correctness of test logic program using the structural properties of Petri nets without coding the test logic programs, where correctness means that the desired output can be obtained by sending or receiving the commands/responses within a constant time under the initial conditions determined uniquely by the test system and SUT. According to our experiment, it is seen that almost all of the logical errors included in the test logic programs used for the experiment can be detected by this method.