We propose a low-noise and low-power dynamic comparator with an offset calibration circuit for Low-Power ADCs. The proposed comparator equips the control circuit in order to switching the comparison accuracy and the current consumption. When high accuracy is not required, current consumption is reduced by allowing the noise increase. Compared with a traditional dynamic comparator, the proposed architecture reduced the current consumption to 78% at 100MHz operating and 1.8V supply voltage. Furthermore, the offset voltage is corrected with minimal current consumption by controlling the on/off operation of the offset calibration circuit.

A compact DC-DC convertor is proposed and fabricated by LTCC technology. Multilayer packaging structure is utilized for size reduction. Measured results are provided to show good performance and validate proposed structure. With the inductor embedded into ferrite substrate, the convertor exhibits advantages of both miniature size and high reliability compared with conventional ones.

Information security has been seriously threatened by the differential power analysis (DPA). Delay-based dual-rail precharge logic (DDPL) is an effective solution to resist these attacks. However, conventional DDPL convertors have some shortcomings. In this paper, we propose improved convertor pairs based on dynamic logic and a sense amplifier (SA). Compared with the reference CMOS-to-DDPL convertor, our scheme could save 69% power consumption. As to the comparison of DDPL-to-CMOS convertor, the speed and power performances could be improved by 39% and 54%, respectively.

We propose a capacitive averaging technique applied to a double-tail latched comparator without a preamplifier for an offset reduction technique. Capacitive averaging can be introduced by considering the first stage of the double-tail latched comparator as a capacitive loaded amplifier. This makes it possible to reduce the offset voltage while preventing an increase in power dissipation. A positive feedback technique is also used for the first stage, which maximizes the effectiveness of the capacitive averaging. The capacitive averaging mechanism and the relationship between the offset reduction and the linearity of the amplifier is discussed in detail. Simulation results for a 90-nm CMOS process show that the proposed technique can reduce the offset voltage by 1/3.5 (3 mV) at a power dissipation of only 45 µW.

A linear voltage-to-current convertor without current mirror circuit is proposed for low distortion applications employing short channel MOSFET's. Twin current sources and current sinks pair of MOSFET's having the same drain-source voltage are employed for a substitute of the current mirror circuits, in order to eliminate the channel length modulation factor of the short channel MOSFET's. HSPICE simulation is shown in order to evaluate the proposed circuits. As an application, a low distortion OTA is realized by employing the proposed linear voltage-to-current convertor with short channel MOSFET's.