This study formulates and solves the wire planning problem with electro-migration and interference using an effective integer linear programming (ILP)-based approach. For circuits without obstacles, the proposed approach obtains a wire planning with the minimum wiring area. An effective approach for estimating the length of feasible routing wire is proposed to handle circuits with obstacles. In addition, the space reservation technique, which allocates the ring of the free silicon space around obstacles, is presented to improve interference among routing wires and on-obstacle wires. For circuits with obstacles, the proposed method minimizes total wiring area and reduces interference. Experimental results show that the integer linear-programming-based approach effectively and efficiently minimizes wiring area of routing wires.

For tracking electromigration induced evolution of voids a diffuse interface model is applied. We assume an interconnect as two-dimensional electrically conducting via which contains initially a circular void. The diffuse interface governing equation was solved applying a finite element scheme with a robust local grid adaptation algorithm. Simulations were carried out for voids exposed to high current. An influence of the void dynamics on the resistance of interconnect is investigated. In the case of the interconnect via it was shown that a migrating void exactly follows the current flow, retaining its stability, but due to change of shape and position causes significant fluctuations in interconnect resistance.

This paper describes the behavior of voids that were formed due to electromigration and diffusion in the interconnections of gold during a DC bias tests of GaAs ICs to current densities in the interconnections of 0.67 106 A/cm2 to 1.27 106 A/cm2 in the high temperature range of 230 to 260. We have found that the voids were formed at the centers in the cross sections of the interconnections and that gold is left around the voids, which means current still flows after the void formation. We have carefully observed the movement of the anode and cathode side edge of the voids during the tests and found that edges moved toward the cathode, in the direction opposite to the electron flow. This direction is constant. Also, the voids are extended, which means that the velocity of the cathode side edge is greater than that of the anode side edge. The velocity of the edges almost proportionally increased with the current density. The constant edge movement direction and the velocity of the edge dependence on the current density suggest that one of the causes of the edge movement is electromigration. The velocity of the edge depends on the distance between the anode side edge of the void and the through hole. The velocity increases in accordance with a decrease in the distance. This means that one of the causes of the edge movement is the diffusion of gold atoms by a concentration and pressure gradient. The GaAs IC failed at almost the same time as the voids appeared. It is important for reliability to prevent the formation of voids caused by electromigration and diffusion.

Via electromigration (EM) performance of aluminum based metallization (AL) systems has been investigated for vias chains of 1500-4000 vias of 1.0 micron diameter. The results show that via EM lifetime can not be enhanced by a simple increase of M2 step coverage in AL/AL vias because the EM induced voids are formed at AL/AL via interface where electrons flow from Ml to M2 even in the case of very poor M2 step coverage. The voids are induced by the boundary layer in AL/AL vias, where a temperature gradient causes discontinuity of aluminum atoms flux. The failure location is not moved though via EM lifetime can be improved by controlling stress in passivation, sputter etch removal thickness and grain size of the first metal. Next, the effect of the boundary layer are eliminated by depositing titanium under the second aluminum or depositing WSi on the first aluminum. In the both cases, via EM lifetime are improved and the failure locations are changed. Especially WSi layer suppresses the voids formation rather than titanium. Models for the failure mechanism in each metallization system are further discussed.

A new effect of barrier metal laid under 1st aluminum layer on electromigration has been found in interconnect vias. This effect can be explained by Si nodules at vias. Stress induced open failure occurred at viaholes and depends on the size of the vias. Stress-migration at vias can be prevented by TiN barrier metal between 1st and 2nd metals. Reliability of electro- and stress-migration at interconnect vias can be explosively improved by using TiN barrier metal.

The performance of copper interconnects formed by the low-kinetic-energy ion bombardment process has been investigated. The copper films formed on SiO2 by this technology under a sufficient amount of ion energy deposition exhibit perfect orientation conversion from Cu (111) to Cu (100) upon post-metallization thermal annealing. We have discovered such crystal orientation conversion is always accompanied by a giant-grain growth as large as 100 µm. The copper film resistivity decreases due to the decrease in the grain boundary scattering, when the giant-grain growth occurs in the film. The resistivity of giant-grain copper film at a room temperature is 1.76 µΩcm which is almost equal to the bulk resistivity of copper. Furthermore, a new-accelerated electromigration life-test method has been developed to evaluate copper interconnects having large electromigration resistance within a very short period of test time. The essence of the new method is the acceleration by a large-current-stress of more than 107 A/cm2 and to utilize the self heating of test interconnect for giving temperature stress. In order to avoid uncontrollable thermal runaway and resultant interconnect melting, we adopted a very efficient cooling system that immediately removes Joule heat and keeps the interconnect temperature constant. As a result, copper interconnects formed by the low-kinetic-energy ion bombardment process exhibit three orders of magnitude longer lifetime at 300 K than Al alloy interconnects.