We propose a new scanning method for image signals using a tree structure of automata. The tree is scanned selectively along the signal path for realizing both lower power consumption and a kind of image compression by skipping nonactive elements. We designed the node automata along with photo-detectors of 3232 in a 7.2 mm7.2 mm chip using a 1.5µm CMOS technology. We demonstrate applications of the tree structure using its feature of selective activation; a moving picture compression using inter-frame difference, an adaptive resolution scan like human eyesight and a motion compensation as examples.

Discussed here is progress achieved in the development of video codec LSIs.First, the amount of computation for various standards, and signal handling capability (throughput) and power dissipation for video codec LSIs are described. Then, general technologies for improving throughtput are briefly summarized. The paper also reviews three approaches (i.e., video signal processor, building block and monolithic codes) for implementing video codes standards. The second half of the paper discusses various high-throughput technologies developed for programmable Video Signal Processor (VSP) LSIs. A number of VSP LSIs are introduced, including the world's first programmable VSP, developed in February 1987 and a monolithic codec ship, built in February 1993 that is sufficient in itself for the construction of a video encoder for encoding full-CIF data at 30 frames per second. Technologies for reduction of power dissipation while keeping maintaining throughput are also discussed.

In arithmetic units multiplication is a very important operation. It is a common approach to use the modified Booth's algorithm to reduce the number of partial products in a multiplication and speed it up. In this letter we show two circuits that fuse the usually separate functions of generating the partial products and selecting them. The circuits designed in DPL (Double Pass-transistor Logic) are bigger in MOS transistors, but are faster and, function at higher frequencies than a typical CMOS implementation. One of our circuits also has lower power consumption.

A motion compensation LSI for realtime MPEG1/H.261 video encoding has been developed. This LSI employs a compact motion estimator that consists of vector search array processors. Furthermore, an efficient motion vector search strategy that enables bidirectioanl searches with a -16.0/+15.5 pels range is adopted to maintain encoded picture quality. The adopted strategy takes two steps. The first step is the full search for 2-pel precision vectors within the range of 16 pels. A 4-to-1 sub-sampling technique with a low pass filter is employed in this step. The second step is the full search for half-pel precision vectors within a 1.0 pels search range centered on the location pointed by the best 2-pel precision vectors. This strategy is compared with the exhaustive-search strategy. It is shown that the number of operations and external memory access cycles are reduced to 1/11 and 1/2, respectively, while differences of the signal to noise ratios obtained by simulation are within 0.2 dB. Those reductions contribute to lowering power dissipation. The array processors calculate the values of distortion. They accumulate the absolute differences between current and reference data with a feedback loop to keep the number of processor elements equal to the number of pels in a row of the current block. Multiple reference data buses and a delay line in the feedback loop have been introduced for efficient calculation. In addition, cascade connection of the array processors is studied to shorten calculation periods. This LSI controls input frames reordering buffers and reference frames buffers. It generates the prediction and the prediction error blocks as well as the motion vectors. AC power of current blocks and the values of distortion are obtained for the bit rate control. This LSI is fabricated using 0.8 µm 2-level metal CMOS technology and dissipates 2.0 W from 5 V supply at 36 MHz.

In this paper, a new optimum input encoding algorithm with m-out-of-2m code which is called Half-Hot Code is presented. By applying Half-Hot Code to the input encoding in PLA-based digital system, the logic functions of the system turn out to be unate functions, thus, the number of bit-lines of PLA may be reduced. The proposed method further reduces the number of product-lines of PLA optimally. In this code assignment procedure, computed Boolean subspaces satisfying suggeset two conditions are assigned to each partitioned subset of digital input variables which are obtained by disjoint minimization or other techniques. As an experiment to evaluate the method, the state assignment for finite state machines of two-lavel implementation is considered. Specifically, the proposed Half-Hot Code assignment is compared with arbitrary Half-Hot Code assignment. The results show that the optimum encoding is superior to an arbitrary assignment up to about 24% in the number of product-lines of PLA.

In this paper, two models are proposed for the simulation of MPEG video sources in ATM networks. The projected autoregressive (PAR) model is based on the autoregressive (AR) model compensated by a projection function. The projection function is capable of adjusting the histogram generated by the AR model so that it better fits the histogram obtained from real data. The state transition (ST) model is developed on die basis of recording the variation of frame size in a video sequence. Each state denotes the size of a frame and the number of state depends on the degree of correlation between frames. Our results show that the histogram generated by the ST model is almost identical with that of the real data and the PAR model performs better in capturing the property of autocorrelation of real data. When compared with other models, both of the two models demonstrate an excellent property of fitting the complex histogram curve, which was not achieved by the AR model, and preserving the correlation characteristics. A heuristic search algorithm is also proposed to make our modelling processes more efficient.

An Ultra-high-speed (higher than 60 MHz) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-µm semicustom CMOS LSIC technology and a newly developed high-speed ACS circuit. To reduce power consumption of the one-chip Viterbi decoder, a universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been proposed and employed to the developed VLSIC. In addition, a new maximum-likelihood-decision (MLD) circuit for the SST Viterbi decoder has been developed. The total power consumption of the developed chip is reduced to 75% of the conventional one and the developed Viterbi decodar VLSIC achieves a maximum operation speed of 60 MHz. It achieves near theoretical net coding-gain performance for various coding rates.

We present distributed load balancing mechanisms implemented on multiprocessor systems for real time video encoding, which dynamically equalize load amounts among PE's to cope with extensive computing requirements. The loosely coupled multiprocessor system, e.g. a torus connected one, is treated as the objective system. Two decentralized controlled load balancicg algorithms are proposed, and mathematical analyses are provided to obtain some insights of our decentralized controlled mechanisms. We also prove the proposed algorithms are steady and effective theoretically and experimentally.

Subjective quality tests have proven that embedded adaptive differential PCM (ADPCM), known to tolerate information loss through bit dropping, does not maintain sufficient speech quality when directly applied to asynchronous transfer mode (ATM) due to the fixed-length cell transmission scheme unique to ATM. We propose a coding and transmission scheme which enhances the performance by adjusting the embedded ADPCM coding rate according to input speech characteristics, thereby taking advantage of the ATM environment, where the transmission of variable rate sources is feasible. By varying the number of code bits of an embedded ADPCM coder from 6bits per sample, or 48kbps, for blocks of speech with a high prediction gain, to 2bits, or 16kbps, for silent blocks, a good compromise between coding bit rate and speech quality with gradual degradation due to information loss is achieved. The results of subjective evaluation tests showed the speech quality of the proposed scheme to be over 3.5 mean opinion score (MOS) on a scale of 1 to 5 at a cell loss rate of 10%. A prototype of the codec and the ATM cell assembly/disassembly functions were also fabricated using 3 conventional digital signal processors (DSPs) for real-time conversation tests.

The transmission of HDTV signals on digital networks requires adoption of sophisticated compression techniques to limit the bit-rate requirements and to provide a high-quality and reliable services to customers. This paper describes system design and transmission characteristics of an adaptive subband DCT codec that can encode original 1.2Gb/s HDTV signals at 156Mb/s. The performance of the codec was evaluated using motion picture signals. The characteristics obtained with the codec was found to maintain good picture quality.

This paper presents a design of a new multiple-valued matching VLSI processor for high-speed reasoning. It is useful in the application for real-time rule-based systems with large knowledge bases which are programmable. In order to realize high-speed reasoning, the matching VLSI processor can perform the fully parallel pattern matching between an input data and rules. On the based of direct multiple-valued encoding of each attribute in an input data and rules, pattern matching can be described by using only a programmable delta literal. Moreover, the programmable delta literal circuit can be easily implemented using two kinds of floating-gate MOS devices whose threshold voltages are controllable. In fact, it is demonstrated that four kinds of threshold voltages in a practical floating-gate MOS device can be easily programmable by appropriately controlling the gate, the drain and the source voltage. Finally, the inference time of the quaternary matching VLSI processor with 256 rules and conflict resolution circuits is estimated at about 360 (ns), and the chip area is reduced to about 30 percent, in comparison with the equivalent binary implementation.

We consider an asymptotically sparsely encoded associative memory. Patterns are encoded by n-dimensional vectors of 1 and 1 generated randomly by a sequence of biased Bernoulli trials and stored in the network according to Hebbian rule. Using a heuristic argument we derive the following capacities:c(n)ne/4k log n'C(n)ne/4k(1e)log n'where, 0e1 controls the degree of sparsity of the encoding scheme and k is a constant. Here c(n) is the capacity of the network such that any stored pattern is a fixed point with high probability, whereas C(n) is the capacity of the network such that all stored patterns are fixed points with high probability. The main contribution of this technical paper is a theoretical verification of the above results using the Poisson limit theorems of exchangeable events.