Sparse arrays can usually achieve larger array apertures than uniform linear arrays (ULA) with the same number of physical antennas. However, the conventional direction-of-arrival (DOA) estimation algorithms for sparse arrays usually require the spatial smoothing operation to recover the matrix rank which inevitably involves heavy computational complexity and leads to a reduction in the degrees-of-freedom (DOFs). In this paper, a low-complex DOA estimation algorithm by exploiting the discrete Fourier transform (DFT) is proposed. Firstly, the spatial spectrum of the virtual array constructed from the sparse array is established by exploiting the DFT operation. The initial DOA estimation can obtain directly by searching the peaks in the DFT spectrum. However, since the number of array antennas is finite, there exists spectrum power leakage which will cause the performance degradation. To further improve the angle resolution, an iterative process is developed to suppress the spectrum power leakage. Thus, the proposed algorithm does not require the spatial smoothing operation and the computational complexity is reduced effectively. In addition, due to the extention of DOF with the application of the sparse arrays, the proposed algorithm can resolve the underdetermined DOA estimation problems. The superiority of the proposed algorithm is demonstrated by simulation results.

We investigate the utilization of vector registers (VRs) on reducing memory references for single instruction multiple data fast Fourier transform calculation. We propose to group the butterfly computations in several consecutive stages to maximize utilization of the available VRs and take the advantage of the symmetries in twiddle factors. All the butterflies sharing identical twiddle factors are clustered and computed together to further improve performance. The relationship between the number of fused stages and the number of available VRs is then examined. Experimental results on different platforms show that the proposed method is effective.

High-performance FFT processor is indispensable for real-time OFDM communication systems. This paper presents a CORDIC based design of variable-length FFT processor which can perform various FFT lengths of 64/128/256/512/1024/2048/4096/8192-point. The proposed FFT processor employs memory based architecture in which mixed radix 4/2 algorithm, pipelined CORDIC, and conflict-free parallel memory access scheme are exploited. Besides, the CORDIC rotation angles are generated internally based on the transform of butterfly counter, which eliminates the need of ROM making it memory-efficient. The proposed architecture has a lower hardware complexity because it is ROM-free and with no dedicated complex multiplier. We implemented the proposed FFT processor and verified it on FPGA development platform. Additionally, the processor is also synthesized in 0.18 µm technology, the core area of the processor is 3.47 mm2 and the maximum operating frequency can be up to 500 MHz. The proposed FFT processor is better trade off performance and hardware overhead, and it can meet the speed requirement of most modern OFDM system, such as IEEE 802.11n, WiMax, 3GPP-LTE and DVB-T/H.

Based on our previous work, this work presents a complete method for time-domain processing of frequency-domain data with evenly-spaced frequency indices, together with its application. The proposed method can be used to calculate the cross spectral and power spectral densities for the frequency indices of interest. A promising application for the time-domain processing of frequency-domain data, particularly for calculating the summation of frequency-domain cross- and auto-correlations in orthogonal frequency-division multiplexing (OFDM) systems, is studied. The advantages of the time-domain processing of frequency-domain data are 1) the ability to rapidly acquire the properties that are readily available in the frequency domain and 2) the reduced complexity. The proposed fast algorithm directly employs time-domain samples, and hence, does not need the fast Fourier transform (FFT) operation. The proposed algorithm has a lower complexity (required complex multiplications ∼ O(N)) than conventional techniques.

Multi-core processors have been attracting a great deal of attention. In the domain of signal processing for communications, the current trends toward rapidly evolving standards and formats, and toward algorithms adaptive to dynamic factors in the environment, require programmable solutions that possess both algorithm flexibility and low implementation complexity. Reconfigurable architectures have demonstrated better tradeoffs between algorithm flexibility, implementation complexity, and energy efficiency. This paper presents a reconfigurable homogeneous memory-based FFT processor (MBFFT) architecture integrated in a single chip to provide hybrid SISO/MIMO OFDM wireless communication systems. For example, a reconfigurable MBFFT processor with eight processing elements (PEs) can be configured for one DVB-T/H with N=8192 and two 802.11n with N=128. The reconfigurable processors can perfectly fit the applications of Software Defined Radio (SDR) which requires more hardware flexibility.

In UWB systems, data symbols are transmitted and received continuously. The Fast Fourier Transform (FFT) processor must be able to seamlessly process input/output data. This paper presents the design and implementation of a continuous data flow parallel memory-based FFT (CF-PMBFFT) processor without the use of input buffer for pre-loading the input data. The processor realizes a memory space of two N-words and multiple processing elements (PEs) to achieve the seamless data flow and meet the design requirement. The circuit has been fabricated in TSMC 0.18 µm 1P6M CMOS process with the supply voltage of 1.8 V. Measurement results of the test chip shows that the developed CF-PMBFFT processor takes a core area of 1.97 mm2 with a power consumption of 62.12 mW for a throughput rate of 528 MS/s.

This paper proposes a novel robust audio watermarking algorithm to embed data and extract it in a bit-exact manner based on changing the magnitudes of the FFT spectrum. The key point is selecting a frequency band for embedding based on the comparison between the original and the MP3 compressed/decompressed signal and on a suitable scaling factor. The experimental results show that the method has a very high capacity (about 5 kbps), without significant perceptual distortion (ODG about -0.25) and provides robustness against common audio signal processing such as added noise, filtering and MPEG compression (MP3). Furthermore, the proposed method has a larger capacity (number of embedded bits to number of host bits rate) than recent image data hiding methods.

This paper presents a novel high-speed, low-complexity two-parallel 128-point radix-24 FFT/IFFT processor for MB-OFDM ultrawideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using a two-parallel data-path scheme and a single-path delay-feedback (SDF) structure. The radix-24 FFT algorithm is also realized in our processor to reduce the number of complex multiplications. The proposed FFT/IFFT processor has been designed and implemented with 0.18-µm CMOS technology in a supply voltage of 1.8 V. The proposed two-parallel FFT/IFFT processor has a throughput rate of up to 900 Msample/s at 450 MHz while requiring much smaller hardware complexity and low power consumption.

In this paper, we present a new fast Fourier transform (FFT) algorithm to reduce the table size of twiddle factors required in pipelined FFT processing. The table size is large enough to occupy significant area and power consumption in long-point FFT processing. The proposed algorithm can reduce the table size to half, compared to the radix-22 algorithm, while retaining the simple structure. To verify the proposed algorithm, a 2048-point pipelined FFT processor is designed using a 0.18 µm CMOS process. By combining the proposed algorithm and the radix-22 algorithm, the table size is reduced to 34% and 51% compared to the radix-2 and radix-22 algorithms, respectively. The FFT processor occupies 1.28 mm2 and achieves a signal-to-quantization-noise ratio (SQNR) of more than 50 dB.

In this research, a sub-array preconditioner is applied to improve the convergence of conjugate gradient (CG) iterative solver in the fast multipole method and fast Fourier transform (FMM-FFT) implementation on a large-scale finite periodic array antenna with arbitrary geometry elements. The performance of the sub-array preconditioner is compared with the near-group preconditioner in the array antenna analysis. It is found that the near-group preconditioner achieves a little better convergence, while the sub-array preconditioner can be easily constructed and programmed with less CPU-time. The efficiency of the CG-FMM-FFT with high efficient preconditioner has been demonstrated in numerical analysis of a finite periodic array antenna.

Many parallel Fast Fourier Transform (FFT) algorithms adopt multiple stages architecture to increase performance. However, data permutation between stages consumes volume memory and processing time. One FFT array processing mapping algorithm is proposed in this paper to overcome this demerit. In this algorithm, arbitrary 2k butterfly units (BUs) could be scheduled to work in parallel on n=2s data (k=0,1,..., s-1). Because no inter stage data transfer is required, memory consumption and system latency are both greatly reduced. Moreover, with the increasing of BUs, not only does throughput increase linearly, system latency also decreases linearly. This array processing orientated architecture provides flexible tradeoff between hardware cost and system performance. In theory, the system latency is (s2s-k)tclk and the throughput is n/(s2s-ktclk), where tclk is the system clock period. Based on this mapping algorithm, several 18-bit word-length 1024-point FFT processors implemented with TSMC0.18 µm CMOS technology are given to demonstrate its scalability and high performance. The core area of 4-BU design is 2.9911.121 mm2 and clock frequency is 326 MHz in typical condition (1.8 V,25). This processor completes 1024 FFT calculation in 7.839 µs.

This paper presents a new high-speed three-dimensional (3-D) object recognition system based on two-dimensional (2-D) chain code matching. An observed 3-D object is precisely represented by a 2-D chain code sequence from the discrete surface points of the 3-D object, so that any complex objects can be recognized precisely. Moreover, the normalization procedures such as translation, rotation of 3-D objects except scale changes can be performed systematically and regularly regardless of the complexity of the shape of 3-D objects, because almost all the normalization procedures of 3-D objects are included in the 2-D chain code matching procedure. As a result, the additional normalization procedure become only the processing time for scale changes which can be performed easily by normalizing the length of the chain code sequence. In addition, the fast fourier transformation (FFT) is applicable to 2-D chain code matching which calculates cross correlation between an input object and a reference model, so that very fast recognition is performed. In fact, it is demonstrated that the total recognition time of a 3-D ofject is estimated at 5.35 (sec) using the 28.5-MIPS SPARC workstation.