This paper proposes a large capacity high-speed file memory system implemented with wafer scale RAM which adopts a novel defect-tolerant technique. Based on set-associative mapping, the defective memory blocks on the wafer are repaired by switching with the spare memory blocks. In order to repair the clustered defective blocks, these are permuted logically with other blocks by adding some constant value to the input block addresses. The defective blocks remaining even after applying the above two methods are repaired by using error control codes which correct soft errors induced by alpha particles in an on-line operation as well as hard errors induced by the remaining defective blocks. By using the proposed technique, this paper demonstrates a large capacity high-speed WSI file memory system implemented with high fabrication yield and low redundancy rate.

This paper proposes a reconfigurable parallel processor based on a two-dimensional linear celular automaton model. The processor based on the model can be reconfigured quickly by utilizing the characteristics of the automaton used for its model. Moreover, the processor has short data path length between processing elements compared with the length of the processor based on one-dimensional linear cellular automaton model which has been already discussed. The processing elements of the processor based on the two-dimensional linear cellular automaton model are regarded as cells and the operational states of the processor are treated as the states of the automaton. When faults are detected, the processor can be reconfigured by changing its state under the state transition function of the processor determined by the weighting function of the automaton model. The processor can be reconfigured within a clock period required for making a state transition. This processor is extremely effective for real-time data processing systems required high reliability.

The Memory-Based Reasoning (MBR) is one of the mainstay approaches in massively parallel artificial intelligence research. However, it has not been explored from the viewpoint of hardware implementation. This paper demonstrates high robustness of the MBR, which is suitable for hardware implementation using Wafer Scale Integration (WSI) technology, and proposes a design of WSI-MBR hardware. The robustness is evaluated by a newly developed WSI-MBR simulator in the English pronunciation reasoning task, generally known as MBRTalk. The results show that defects or other fluctuations of device parameters have only minor impacts on the performances of the WSI-MBR. Moreover, it is found that in order to get higher reasoning accuracy, the size of the MBR database is much more crucial than the computation resolution. These features are proved to be caused by the fact that MBR does not rely upon each single data unit but upon a bulk data set. Robustness in the other MBR tasks can be evaluated in the same manner as discussed in this paper. The proposed WSI-MBR processor takes advantage of benefits discovered in the simulation results. The most area-demanding circuits--that is, multipliers and adders--are designed by analog circuits. It is expected that the 1.7 million processors will be integrated onto the 8-inch silicon wafer by the 0.3 µm SRAM technology.

A typical fault-tolerance technique of systolic arrays is to include redundant processors and links so that the array is reconfigurable when some processors fail. Another typical technique is to implement each processor by a majority voter and N (N3) copies of processors so that the faults of up to N-2 copies of processors can be masked without reconfiguration. This paper proposes a systolic linear array called reconfigurable modular redundant linear array (RMA) that combines these techniques with N4. When up to 2 copies of each processor fail in RMA, the faults can be masked without reconfiguration. When some voters or more than 2 copies of a processor fail, RMA can be reconfigured by specifying a new switch pattern. In order to perform reconfiguration efficiently, we present a reconfiguration algorithm with time complexity O (n), where n is the number of processors in RMA.

In developing the SXO operating system for the SURE SYSTEM 2000 continuous operation system, we aimed to create an unprecedentedly high software and hardware fault tolerance. We devised a fault tolerant architecture and various methodologies to ensure fault tolerance. We implemented these techniques systematically throughout operating system development. In the design stage, we developed a design methodology called the recovery process chart to verify that recovery mechanisms were complete. In the manufacturing stage, we applied the concept of critical routes to recovery and other processes essential to high dependability. We also developed a method of finding critical routes in a recovery process chart. In the test stage, we added an artificial software fault injection mechanism to the operating system. It generates various reproducible errors at appropriate times and reduces the number of personnel needed for test, making system reliability evaluation easy.