Graph layouts reveal global or local structures of graph data. However, there are few studies on assisting readers in better reconstructing a graph from a layout. This paper attempts to generate a layout whose edges can be reestablished. We reformulate the graph layout problem as an edge classification problem. The inputs are the vertex pairs, and the outputs are the edge existences. The trainable parameters are the laid-out coordinates of the vertices. We propose a binary classification-based graph layout (BCGL) framework in this paper. This layout aims to preserve the local structure of the graph and does not require the total similarity relationships of the vertices. We implement two concrete algorithms under the BCGL framework, evaluate our approach on a wide variety of datasets, and draw comparisons with several other methods. The evaluations verify the ability of the BCGL in local neighborhood preservation and its visual quality with some classic metrics.

Due to the structure complexity, it is difficult to display structure of large-scale network fully. To solve the problem, this paper research on network simplification and accelerating drawing. Specific research content includes accelerated network layout based on quadtree and community geometric constrain, aiming to provide overall situation perception of network topology. Experiment results show that this method can quickly visualize complex structure of large-scale network, and present overall situation and structural characteristics of the network by clear and understandable visual expression, and contribute to mining and awareness of network connection mode and structural characteristics.

In this paper, we present a novel force-directed method for automatically drawing intersecting compound mixed graphs (ICMGs) that can express complicated relations among elements such as adjacency, inclusion, and intersection. For this purpose, we take a strategy called unified simplification that can transform layout problem for an ICMG into that for an undirected graph. This method is useful for various information visualizations. We describe definitions, aesthetics, force model, algorithm, evaluation, and applications.

Temperature-tracking is becoming of paramount importance in modern electronic design automation tools. In this paper, we present a deterministic thermal placement algorithm for standard cell based layout which can lead to a smooth temperature distribution over the die. It is mainly based on Fiduccia-Mattheyses partition scheme and a former substrate thermal model that can convert the known temperature constraints into the corresponding power distribution constraints. Moreover, a kind of force-directed heuristic based on cells' power consumption is introduced in the above process. Experimental results demonstrate a comparatively uniform temperature distribution and show a reduction of the maximal temperature on the die.

This paper describes a hybrid force-directed self-organizing neural network approach to printed circuit board (PCB) placement with consideration of electromagnetic compatibility (EMC). In most of the conventional PCB automatic placement algorithms, the only factor considered in the objective function is minimized total net length. However, for today's high speed and high density PCB, EMC compliance cannot be met by such single objective. To tackle this problem, the presented algorithm takes EMC into consideration, besides component overlap and minimized total net length. These factors are optimized by means of an adapted self-organizing map. Comparison of simulated placement results as well as actual measurements with commercial softwares confirms the effectiveness of the proposed method.