The methodology for latchup-free design in bipolar and PMOS merged gates, so-called BiPMOS gates, is considered. Although BiPMOS gates can provide higher switching characteristics than conventional, individually drawn, BiCMOS gates even when the supply voltage is reduced, the general methodology to prevent latchup has been lacking. This paper presents an approximate, but sufficiently correct, mathematical technique to solve the Laplace equation, which gives the distribution of latchup trigger current for the given BiPMOS drawings. It is shown that the resistances of the collector plug and the spreading resistance under the base-collector junction greatly influence latchup, and that the well-emitter overlapping space becomes a problem in the case of a single collector. The distribution of latchup triggering current for the double-emitter double collector NPN transistor indicates the optimum position of the source diffusion area.

This paper presents the dynamics of heavy-ion induced latchup turn-on behavior in CMOS structures using a three-dimensional and transient device simulation. The three-dimensional effects of parasitic devices in a CMOS structure during latchup turn-on are discussed in detail when a heavy-ion strikes the CMOS structure. For different incident types, the dynamics of latchup turn-on behaviors are also simulated. Moreover, latchup immunities of the CMOS structure obtained by two- and three-dimensional calculations are compared for the different incident types. This result suggests that the rough relation between latchup immunity and heavy-ion incident energy can be estimated using a two-dimensional simulation.