This paper discusses the design of an ITS to realize a load-oriented tutoring to enhance the student's explanation understanding. In the explanation understanding, it is to be hoped that a student not only memorizes the new information from an explanation, but also relates the acquired information with his/her own knowledge to recognize what it means. This relating process can be viewed as the one in which the student structures his/her knowledge with the explanation. In our ITS, we regard the knowledge-structuring activities as the explanation understanding. In this paper, we propose an explanation, called a load-oriented explanation, with the intention of applying a load to the student's knowledge-structuring activities purposefully. If the proper load is applied, the explanation can induce the student to think by himself/herself. Therefore he/she will have a chance of gaining the deeper understanding. The important point toward the load-oriented explanation generation is to control the load heaviness appropriately, which a student will bear in understanding the explanation. This requires to estimate how an explanation promotes the understanding activities and how much the load is applied to the activities. In order to provide ITS with the estimation, we have built an Explanation Effect Model, EEM for short. Our ITS consists of an explanation planner and a self-explanation environment. The planner generates the load-oriented explanation based on EEM. The system also makes a student explain the explanation understanding process to himself/herself. Such self-explanation is useful to let the student be conscious of the necessity of structuring his/her knowledge with the explanation. The self-explanation environment supports the student's self-explanation. Furthermore, if the student reaches an impasse in self-explaining, the planner can generate the supporting explanation for the impasse.

The ray-tracing algorithm can synthesize very realistic images. However, the ray tracing is very time consuming. To solve this problem, a load balancing strategy using temporal coherence between images in an animation is presented for balancing computational loads among processing elements of a parallel processng system. Our parallel processing model is based on a space subdivision method for the ray-tracing algorithm. A subdivided object space is distributed among processing elements of the parallel system. To clarify the effectiveness of the load balancing strategy, we examine the system performance by computer simulation.

Toward the age of ultra-high-density digital ULSI systems, the development of new integrated circuits suitable for an ultimately fine geometry feature size will be an important issue. Resonant-tunneling (RT) diodes and transistors based on quantum effects in deep submicron geometry are such kinds of key devices in the next-generation ULSI systems. From this point of view, there has been considerable interests in RT diodes and transistors as functional devices for circuit applications. Especially, it has been recognized that RT functional devices with multiple peaks in the current-voltage (I-V) characteristic are inherently suitable for implementing multiple-valued circuits such as a multiple-state memory cell. However, very few types of the other multiple-valued logic circuits have been reported so far using RT devices. In this paper, a new multiple-valued programmable logic array (MVPLA) based on RT devices is proposed for the next-generation ULSI-oriented hardware implementation. The proposed MVPLA consists of 3 basic building blocks: a universal literal circuit, an AND circuit and a linear summation circuit. The universal literal circuit can be directly designed by the combination of the RT diodes with one peak in the I-V characteristic, which is programmable by adjusting the width of quantum well in each RT device. The other basic building blocks can be also designed easily using the wired logic or current-mode wired summation. As a result, a highdensity RT-diode-based MVPLA superior to the corresponding binary implementation can be realized. The device-model-based design method proposed in this paper is discussed using static characteristics of typical RT diode models.

Based on distributed artificial intelligence technology, the paper proposes a distributed expert system for distribution system planning. The developed expert system is made up of a set of problem-solving agents that autonomously process local tasks and cooperatively interoperate with each other by a shared database in order to reach a proper distribution plan. In addition, a two-level control mechanism composed of local-control and meta-control is also proposed to achieve a high degree of goodness in distribution system planning. To demonstrate its effect, the distributed expert system is implemented on basis of NASA's CLIPS and SUN's RPC and applied to the planning of distribution system in Taiwan. Test results indicate that the distributed expert system assists system planners in making an appropriate plan.

An active feedback resonator (AFR) is a kind of circuit which functions as a high unloaded Q resonator. The AFR employs an active feedback loop which compensates for the energy loss of a conventional microwave resonator. Owing to an active element in the AFR, thermal noise should be taken into account when designing the AFR. In order to simplify a circuit design using the AFR we introduced noise temperature (Tn) for the AFR. In addition, we describe the AFR design which gives minimum noise temperature. Finally, the noise temperature, measured in an AFR as a band elimination filter, is compared with the theoretical value to evaluate the AFR.

This paper introduces the new application specific architecture RHINE (Reconfigurable Hierarchical Image Neo-multiprocessor Engine) that is a multiprocessor system for moving picture CODEC. The array processor is known to be originally suited for data parallel processing such as image signal processing which requires vast amount of computations and has the identical instruction sequences on data. However, the moving picture CODEC algorithm suffers from the large load imbalance in the processings on multi-processors with the separated sub-images. Some load balancing techniques are indispensable in such applications for the highest speed-up. RHINE gives one of the optimal solutions for such a load balancing due to its feature of the self reconfigurable architecture. RHINE consists of Block Processing Units (BPU) hierarchically, in each of which has a common bus architecture of multiprocessors with a block memory. Processors in a BPU move to the other BPU according to the load imbalance between BPUs by switching the bus connection between BPUs. The advantage of RHINE architecture is demonstrated by showing performance simulations for real moving pictures.

A non-profit satellite communication network is desired to be configured by using low cost earth stations in the field of education, research and health in the Pacific region. This paper proposes the following concept as one of the tools to realize such a network: (a) A hitchhiker transponder dedicated to the network, and (b) The volunteer group prepares earth stations. A preliminary system design shows that the S band hitchhiker payload is most appropriate and has the weight of about 3kg. The feasibility of manufacturing earth stations by a volunteer group is examined through the experiment using ETS-V satellite. The parameters of the hitchhiker payload are re-examined on the basis of the experience of the experiment.

In this paper, optimal static load balancing in a tree hierarchy network that consists of a set of heterogeneous host computers is considered. It is formulated as a nonlinear optimization problem. We study the effects of the link communication time on the optimal link flow rate (i.e., the rate at which a node forwards jobs to other nodes for remote processing), the optimal node load (i.e., the rate at which jobs are processed at a node), and the optimal mean response time, by parametric analysis. We show that the entire network can be divided into several independent sub-tree networks with respect to the link flow rates and node loads. We find that the communication time of a link has the effects only on the link flow rates and the loads on nodes that are in the same sub-tree network. The increase in the communication time of a link causes the decrease in the link flow rates of its descendant nodes, its ancestor nodes and itself, but causes the increase in the link flow rates of other nodes in the same sub-tree network. It also causes the increase in the loads of its descendant nodes and itself, but causes the decrease in the loads of other nodes in the same sub-tree network. In general, it causes the increase in the mean response time.

Modeling and performance analysis have played an important role in the economical design and efficient operation of switching systems, and is currently becoming more important because the switching systems should handle a wide range of traffic characteristics, meeting the grade of service requirements of each traffic type. Without these techniques we could no longer achieve economy and efficiency of the switching systems in complex traffic characteristic environments. From the beginning of research on electronic switching systems offering circuit-switched applications, Stored Program Control (SPC) technology has posed challenges in the area of modeling and performance analysis as well as queueing structure, efficient scheduling, and overload control strategy design. Not only teletraffic engineers and performance analysts, but also queueing theorists have been attracted to this new field, and intensive research activities, both in theory and in practice, have continued over the past two decades, now evolving to even a broader technical field including traditional performance analysis. This article reviews a number of important issues that have been raised and solved, and whose solutions have been reflected in the design of SPC switching systems. It first discusses traffic problems for centralized control systems. It next discusses traffic problems inherent in distributed switching systems.

Cell losses due to statistical multiplexing of bursty traffic in ATM networks tend to be in clusters rather than uniformly scattered. Since the quality of service for users is quite sensitive to such bursty losses, it is necessary to characterize the temporal behavior of cell loss. This paper reports results obtained from investigating overload period and underload period in an ATM multiplexer with heterogeneous burst traffic input, using a bufferless model. The overload period is defined as the time interval when the instantaneous bit rate exceeds the output link capacity. With the bufferless model, we assume that all the instantaneous bit rate exceeding the link capacity is lost, and the loss rate is called "virtual cell loss probability". The virtual cell loss probability during the overload period, average overload period and underload period durations are analyzed. Numerical results show that the cell loss probability in overload periods and the average duration of overload periods (normalized by burst duration) are not very sensitive to link load or average rate/peak rate ratio of the burst, and that they are approximately on the order of peak bandwidth/link capacity ratio for the multiplexed burst. Furthermore, it is also shown that the mean underload duration is simply given as the inverse of the overall cell loss probability multiplied by the constant value inherently determined by peak bandwidth and link capacity. With these observations, applications to the call acceptance control using these measures are also presented.

Processors are important resources of stored program control (SPC) switching systems, and estimation of their workload level is crucial to maintaining service quality. Processor utilization is measured as processor usage per unit time, and workload level is usually estimated from measurement of this utilization during a given interval. This paper provides an approximate distribution of processor utilization of SPC switching systems, and it provides a method for designing an overload detection scheme. This method minimizes the observation interval required to keep overload detection errors below specified values. This observation interval is obtained as an optimal solution of a linear programming.

The effects of changing system parameters on job scheduling policies are studied for load balancing of multi-class jobs in a distributed computer system that consists of heterogeneous host computers connected by a single-channel communications network. A job scheduling policy decides which host should process the arriving jobs. We consider two job scheduling policies. The one is the overall optimal policy whereby jobs are scheduled so as to minimize the overall mean job response time. Tantawi and Towsley obtained the algorithm that gives the solution of the policy in the single class job environment and Kim and Kameda extended it to the multiple job class environment. The other is the individually optimal policy whereby jobs are scheduled so that every job may feel that its own expected response time is minimized. We can consider three important system parameters in a distributed computer system: the communication time of the network, the processing capacity of each node, and the job arrival rate of each node. We examine the effects of these three parameters on the two load balancing policies by numerical experiment.

Optimal static load balancing problems in open BCMP queueing networks with state-independent arrival and service rates are studied. Their examples include optimal static load balancing in distributed computer systems and static routing in communication networks. We refer to the load balancing policy of minimizing the overall mean response (or sojourn) time of a job as the overall optimal policy. We show the conditions that the solutions of the overall optimal policy satisfy and show that the policy uniquely determines the utilization of each service center, the mean delay for each class and each path class, etc., although the solution, the utilization for each class, the mean delay for all classes at each service center, etc., may not be unique. Then we give tha linear relations that characterize the set whose elements are the optimal solutions, and discuss the condition wherein the overall optimal policy has a unique solution. In parametric analysis and numerical calculation of optimal values of performance variables we must ensure whether they can be uniquely determined.

This paper describes the design of a 38-GHz high power MMIC amplifier using an improved load-pull technique. We improved the load-pull technique accuracy by using MMIC transtormers to match the input and output impedances of a GaAs MESFET to about 50 ohms. We used this technique to measure the large-signal load impedance of a FET with a 600-µm-wide gate. Using the data obtained, we developed an MMIC amplifier composed of two of these FET cells. At 38 GHz, the amplifier has an output power of 23.5 dBm for a 1 dB gain compression level.