A fuel cell energy system is under development for supply of generated electrical energy to telecommunications equipment. It is a cogeneration system; the heat energy recovered is used to cool the telecommunications equipment. For this system, a method is described for controlling a new DC interconnection converter. Its DC interconnection characteristics are also discussed. The new converter controls its input current to the fuel cell rated current at maximum and can operate stably even when the fuel cell voltage decreases. This allows good DC interconnection characteristics to be obtained in both the steady state and the transient state.

Workers involved in software projects are unlike those working on a production line in a manufacturing field usually engaged in plural work (that is, not only main development work but also various other work), concurrently. Such other work might put pressure on the schedule of the whole project. Therefore, to manage the whole project, not only main development work but also various other work should be dealt with as management objects and workers' workload should be taken into consideration (that is, who is doing what work at what workload at what time). This paper proposes a framework for workload management facilities for managing software projects. This framework proposes to relate not only main development work but also various other work and each work step within cooperative work to the workers. This paper also shows the behavior of the facilities by using an example and shows its usefulness based on the application of a prototype system. Using this system, users can assign work to workers by simulating workers' workload. These facilities help managers grasp workers' workload as well as help workers grasp their assigned work.

A partial buffer sharing scheme is proposed as loss-priority control for a finite buffer with batch inputs. A partial batch acceptance strategy is used for a batch arriving at a finite buffer. Customer loss probabilities for high- and low-priority customers are derived under this batch acceptance strategy, using a supplementary variable method that is a standard tool for queueing analysis. A comparison of the partial buffer sharing scheme and a system without loss-priority control is made in terms of admissible offered load.

In this paper, a new overload control strategy is proposed for a call control processor (CCP) in the base station controller (BSC) and processor utilization is measured. The proposed overload control strategy can regulate the call attempts by adopting measured processor utilization. A function, specifically a linear interpolation function based on Inverse Transform theory is used to convert controlled predictive average load rate in a call rejection rate. Then a call admission rate is obtained from the call rejection rate. Simulation shows that the proposed algorithm yields better performance than the conventional algorithm does under the heavy transient overload status in terms of call admission rate.

Differences in the behavior of dispenser cathodes and oxide cathodes in laminar-flow type and crossover type electron guns were investigated by experiments and simulations under high-current-density conditions. When an oxide cathode is operated under such conditions, the heating effect due to Joule heat in the oxide layer exceeds the cooling effect, depending on the product of the work function and the cathode current, resulting in a rise in the cathode temperature. This rise in cathode temperature aggravates deterioration of emission characteristics during the life of an oxide cathode. In the case of the dispenser cathode, however, the cathode temperature decreases under high-current-density conditions. When an oxide cathode in a crossover type electron gun is operated, equipotential surfaces are formed in the curved surface in the oxide layer. The formation of an equipotential surface leads to relaxation of the loading. It is considered that this is the reason for the longer life of an oxide cathode in a crossover type electron gun than that of an oxide cathode in a laminar-flow type electron gun.

The new technique for reducing the load latency is presented. This technique, named tunneling-load, utilizes the register specifier buffer in order to reduce the load latency without fetching the data cache speculatively, and thus eliminates the drawback of any load address prediction techniques. As a consequence of the trend toward increasing clock frequency, the internal cache is no longer able to fill the speed gap between the processor and the external memory, and the data cache latency degrades the processor performance. In order to hide this latency, several techniques predicting the load address have been proposed. These techniques carry out the speculative data cache fetching, which causes the explosion of the memory traffic and the pollution of the data cache. The tunneling-load solves these problems. We have evaluated the effects of the tunneling-load, and found that in an in-order-issue superscalar platform the instruction level parallelism is increased by approximately 10%.

We will present a partial scan design method based on n-fold line-up structures in order to achieve high fault efficiency and reduce test pattern generation time for practical LSIs. We will also present a partial scan design method based on the state justification of pure load/hold FFs in order to achieve high fault efficiency and reduce the number of scan FFs for practical LSIs with lots of load/hold FFs. Experimental results for practical LSIs show that our presented methods can achieve high fault efficiency (more than 99%) and reduce the number of scan FFs for the LSI with lots of load/hold FFs.

In high-frequency operation, it is difficult to obtain a large tuning range in load-pull measurement due to losses in the tuning network and RF-probes. In this paper, a low-loss on-wafer-tuning load-pull method is proposed. The output matching network consists of two CPWs connected to a FET output terminal. The impedance of the network can be controlled by changing the effective length of the CPWs by replacing RF-probes and removing air-bridges. To confirm the validity of this load-pull method, a K-band high-efficiency MMIC power amplifier has been designed using the method and fabricated. The amplifier demonstrates performance of 19. 5-dBm saturated output power, 12. 5-dB linear gain and 49. 3% maximum power-added efficiency (PAE) at Vds = 3 V for 26 GHz operation. At 1-dB gain-compression, the PAE is still as high as 44%. This high PAE result clearly indicates that the proposed method is a useful tool for designing power amplifiers, especially those for use in high-frequency (e.g. K-band) operation.

As MOSFET sizes and wire widths become very small in recent years, influence of resistive component of interconnects on the estimation of propagation delay and power dissipation can no longer be neglected. In this paper we present formulas of output waveform at driving point and short-circuit power dissipation for static CMOS logic gates driving a CRC π load. By representing the short-circuit current and the current flowing in the resistance of a CRC π load by piece-wise linear functions, a closed-form formula is derived. On the gate delay the error of our formula is less than 8% from SPICE in our experiments. These formulas will contribute to faster estimation of circuit speed and power dissipation of VLSI chips on timing level simulators.

In this paper, we analyze overload and stability in the charge-pump phase locked loop (PLL). We propose a new computational model that can be applied for the precise estimation of the physical limits of charge-pump, the leakage current of loop filter and waveform distortion of charge-pump PLL operating in high speed. We derive the exact mathematical expressions of the parameters describing the steady-state behavior of the PLL as well as the transient-state behavior. Performance comparisons with the conventional model are provided through numerical results. Algorithms for approximate analysis is also provided. The new model is particularity useful for analyzing the cases that the charge-pump PLL operates in high- speed or the loop filter has large leakage current.

In this paper, we propose two mechanisms for the priority added automatic call gapping method under the fairness scheme and analyze the effect of those mechanisms. Both mechanisms provide good overload controllability and work well on the priority calls. We also define a measure of priority achievement. Both mechanisms show good performance on the pass probability and priority achievement.

The reduction of coupling between two wire antennas operating at different frequencies on an infinite ground plane is considered. An impedance loaded slot is introduced between the two antennas. A coupling coefficient and a transmission coefficient are used to evaluate the coupling behavior. It is found that by an appropriate choice of the slot length, location and load impedance the coupling coefficient can be reduced significantly. The problem is analyzed by the method of moments. Port parameters are used to relate a feed port, load ports on the two wire antennas and a load port on the slot. In so doing, a large amount of computation time is saved in calculating the antenna characteristics for various loads on the slot.

In this paper we propose a new method for parallel execution of Prolog programs and present its implementation on a distributed memory parallel computer, Fujitsu AP1000. In our method a number of processes (named Prolog engines) explore different branches of a search tree (named tasks) in parallel, which is the same as OR-parallelism. Unlike OR-parallelism, the mapping between Prolog engines and tasks is statically determined like data parallelism. Each Prolog engine can decide which task is executed by the engine without communicating with the other engines. In many search problems, however, such static task mapping may cause imbalance on the processing time of each engine since the computational costs to explore branches may vary substantially. To cope with this issue, we devise a method to adjust the task imbalance by periodical exchanging how many tasks were processed for each engine. Also for reducing communication overhead in load balancing, we limit the scope of engines that exchange the load information each other. The effectiveness of our method is evaluated by measuring execution times for N Queens and the Traveling Salesman Problem on the AP1000. Using 512 processors, we obtained 355-fold speedup for N Queens and 343-fold speedup on the Traveling Salesman Problem.

A large scale simulation for polymer chains in good solvent is performed. The implementation technique for efficient parallel execution, optimization, and load-balancing are discussed on this practical application. Finally, a simple performance model is proposed.

Because a massively parallel computer processes vast amounts of data and generates many access requests from multiple processors simultaneously, parallel secondary storage requires large capacity and high concurrency. One effective method of implementation of such secondary storage is to use disk arrays which have multiple disks connected in parallel. In this paper, we propose a parallel file access method named DECODE (dynamic express changing of data entry) in which load balancing of each disk is achieved by dynamic determination of the write data position. For resolution of the problem of data fragmentation which is caused by the relocation of data during a write process, the concept of "Equivalent Area" is introduced. We have performed a preliminary performance evaluation using software simulation under various access statuses by changing the access pattern, access size and stripe size and confirmed the effectiveness of load balancing with this method.

Narrow-band ISDN services may experience nonstationary traffic conditions. Therefore, switch design should take account of these conditions. We propose new performance measures for switching systems and describe a traffic model, which is a mixture of stationary Poissonian traffic and momentarily focused traffic. On the basis of this model, performance measures are determined so as to satisfy grade of service requirements that are in effect during some short interval after the momentarily focused traffic enters the system. We also propose an overload control scheme that uses these new performance measures. Finally, we show practical and numerical examples for the performance measures and overload control scheme.

As current-voltage characteristics of GaAs MESFET differ from those of BJT and MOSFET and n-channel FET is only practically in use, the development of GaAs MESFET analog integrated circuits is left behind. In this paper, two circuit techniques to improve the performance of GaAs MESFET analog circuits are provided. The one is to realize a high impedance active load circuit which dose not need CMFB (Common Mode Feed Back) to achieve stable DC biasing point. The other is to cancel the harmonic destortion caused by nonlinear characteristics of GaAs MESFETs. As an application example of the proposed circuits, biquad low-pass and band-pass filters are realized and simulated by HSPICE to verify the validity of the proposed method.

In this paper, we evaluate the throughput performance of CDMA Slotted ALOHA systems. To improve the throughput performance, we employ the Quasi-synchronous sequences and the Modified Channel Load Sensing Protocol as an access control procedure. As a result, we found a good throughput by the QS-sequences. By employing MCLSP, we can keep the maximum throughput even in high offered load and in the presence of a long access timing delay, which is one of the issue in satellite packet communication systems.

A 3V-50 MHz analog CMOS current-mode continuous-time active filter with a negative resistance load (NRL) is proposed. In order to design a current-mode current integrator, a modified basic current mirror with a NRL to increase the output resistance is employed. The inherent circuit structure of the designed NRL current integrator, which minimizes the internal circuit nodes and enhances the gain bandwidth product, is capable of making the filter operate at the high frequency. The third order Butterworth low pass filter utilizing the designed NRL current integrator is synthesized and simulated with a 1.5 µm CMOS n-well process. Simulation result shows the cutoff frequency of 50 MHz and power consumption of 2.4mW/pole with a 3V power supply.

In this paper, we introduce a parallel algorithm for parsing context-free languages. Our algorithm can handle arbitrary context-free grammars since it is based on Earley's algorithm. Our algorithm can operate on any loosely coupled multiprocessor which can provide a topology of a one-way ring. Our algorithm uses p processors to parse an input string of length n where 1 p n. It is shown that our algorithm requires O(n3/p) time. The algorithm uses a simple job allocation strategy. However, it achieves high load balancing and uses the processors efficiently.