This letter presents a necessary and sufficient condition for a class of quasi-cyclic low-density parity-check (QC LDPC) codes without girth four. Girth-four property of a class of QC LDPC codes is investigated. Good QC LDPC codes without girth four can be constructed by selecting proper shifting factors according to the proposed theorems. Examples are provided to verify the theorems. The simulation results show that the QC LDPC codes without girth four achieve a better BER performance compared with that of randomly constructed LDPC codes.

A new ensemble of low-density parity-check (LDPC) codes for correcting a solid burst erasure is proposed. This ensemble is an instance of a combined matrix ensemble obtained by concatenating some LDPC matrices. We derive a new bound on the critical minimum span ratio of stopping sets for the proposed code ensemble by modifying the bound for ordinary code ensemble. By calculating this bound, we show that the critical minimum span ratio of stopping sets for the proposed code ensemble is better than that of the conventional one with keeping the same critical exponent of stopping ratio for both ensemble. Furthermore from experimental results, we show that the average minimum span of stopping sets for a solid burst erasure of the proposed codes is larger than that of the conventional ones.

In this paper, we propose a method for enhancing performance of a sequential version of the belief-propagation (BP) decoding algorithm, the group shuffled BP decoding algorithm for low-density parity-check (LDPC) codes. An improved BP decoding algorithm, called the shuffled BP decoding algorithm, decodes each symbol node in serial at each iteration. To reduce the decoding delay of the shuffled BP decoding algorithm, the group shuffled BP decoding algorithm divides all symbol nodes into several groups. In contrast to the original group shuffled BP, which automatically generates groups according to symbol positions, in this paper we propose a method for grouping symbol nodes which generates groups according to the structure of a Tanner graph of the codes. The proposed method can accelerate the convergence of the group shuffled BP algorithm and obtain a lower error rate in a small number of iterations. We show by simulation results that the decoding performance of the proposed method is improved compared with those of the shuffled BP decoding algorithm and the group shuffled BP decoding algorithm.

Reducing the power dissipation for LDPC code decoder is a major challenging task to apply it to the practical digital communication systems. In this paper, we propose a low power LDPC code decoder architecture based on an intermediate message-compression technique which features as follows: (i) An intermediate message compression technique enables the decoder to reduce the required memory capacity and write power dissipation. (ii) A clock gated shift register based intermediate message memory architecture enables the decoder to decompress the compressed messages in a single clock cycle while reducing the read power dissipation. The combination of the above two techniques enables the decoder to reduce the power dissipation while keeping the decoding throughput. The simulation results show that the proposed architecture improves the power efficiency up to 52% and 18% compared to that of the decoder based on the overlapped schedule and the rapid convergence schedule without the proposed techniques respectively.

Irregular LDPC codes can achieve better error rate performance than regular LDPC codes. However, irregular LDPC codes have higher error floors than regular LDPC codes. The Ordered Statistic Decoding (OSD) algorithm achieves approximate Maximum Likelihood (ML) decoding. ML decoding is effective to lower error floors. However, the OSD estimates satisfy the parity check equation of the LDPC code even the estimates are wrong. Hybrid decoder combining LLR-BP decoding algorithm and the OSD algorithm cannot also lower error floors, because wrong estimates also satisfy the LDPC parity check equation. We proposed the concatenated code constructed with an inner irregular LDPC code and an outer Cyclic Redundancy Check (CRC). Owing to CRC, we can detect wrong codewords from OSD estimates. Our CRC-LDPC code with hybrid decoder can lower error floors in an AWGN channel. In wireless communications, we cannot neglect the effects of the channel. The OSD algorithm needs the ordering of each bit based on the reliability. The Channel State Information (CSI) is used for deciding reliability of each bit. In this paper, we evaluate the Block Error Rate (BLER) of the CRC-LDPC code with hybrid decoder in a fast fading channel with perfect and imperfect CSIs where 'imperfect CSI' means that the distribution of channel and those statistical average of the fading amplitudes are known at the receiver. By computer simulation, we show that the CRC-LDPC code with hybrid decoder can lower error floors than the conventional LDPC code with hybrid decoder in the fast fading channel with perfect and imperfect CSIs. We also show that combining error detection with the OSD algorithm is effective not only for lowering the error floor but also for reducing computational complexity of the OSD algorithm.

Decoding performance of LDPC (Low-Density Parity-Check) codes is highly dependent on the degree distributions of the Tanner graphs which define the LDPC codes. We compare two LDPC code ensembles, one has a uniform degree distribution and the other a non-uniform one over a BEC (Binary Erasure Channel) and a BSC (Binary Symmetric Channel) thorough DE (Density Evolution). We then derive sufficient conditions on the erasure probability of a BEC and the error probability of a BSC, under which the LDPC code ensembles with uniform degree distributions outperform those with non-uniform degree distributions.

In this paper, we propose a power-efficient LDPC decoder architecture based on an accelerated message-passing schedule. The proposed decoder architecture is characterized as follows: (i) Partitioning a pipelined operation not to read and write intermediate messages simultaneously enables the accelerated message-passing schedule to be implemented with single-port SRAMs. (ii) FIFO-based buffering reduces the number of SRAM banks and words of the LDPC decoder based on the accelerated message-passing schedule. The proposed LDPC decoder keeps a single message for each non-zero bit in a parity check matrix as well as a classical schedule while achieving the accelerated message-passing schedule. Implementation results in 0.18 [µm] CMOS technology show that the proposed decoder architecture reduces an area of the LDPC decoder by 43% and a power dissipation by 29% compared to the conventional architecture based on the accelerated message-passing schedule.

Multi-Edge type Low-Density Parity-Check codes (MET-LDPC codes) introduced by Richardson and Urbanke are generalized LDPC codes which can be seen as LDPC codes obtained by concatenating several standard (ir)regular LDPC codes. We prove in this paper that MET-LDPC code ensembles possess a certain symmetry with respect to their Average Coset Weight Distributions (ACWD). Using this symmetry, we drive ACWD of MET-LDPC code ensembles from ACWD of their constituent ensembles.

We propose transformation of a parity-check matrix of any low-density parity-check code. A code with transformed parity-check matrix is an equivalent of a code with the original parity-check matrix. For the binary erasure channel, performance of a message-passing algorithm with a transformed parity-check matrix is better than that with the original matrix.

In this paper, we propose a partially-parallel LDPC decoder which achieves a high-efficiency message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) The column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently. (ii) The proposed parallel pipelined bit functional unit enables the column operation module to compute every message in each bit node which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay when the row and column operations are performed concurrently. Therefore, the proposed decoder performs the column operations more frequently in a single iterative decoding, and achieves a high-efficiency message-passing schedule within the limited decoding delay time. Hardware implementation on an FPGA and simulation results show that the proposed partially-parallel LDPC decoder improves the decoding throughput and bit error performance with a small hardware overhead.

Irregular Low-Density Parity-Check (LDPC) codes generally achieve better performance than regular LDPC codes at low Eb/N0 values. They have, however, higher error floors than regular LDPC codes. With respect to the construction of the irregular LDPC code, it can achieve the trade-off between the performance degradation of low Eb/N0 region and lowering error floor. It is known that a decoding algorithm can achieve very good performance if it combines the Ordered Statistic Decoding (OSD) algorithm and the Log Likelihood Ratio-Belief Propagation (LLR-BP) decoding algorithm. Unfortunately, all the codewords obtained by the OSD algorithm satisfy the parity check equation of the LDPC code. While we can not use the parity check equation of the LDPC code to stop the decoding process, the wrong codeword that satisfies the parity check equation raises the error floor. Once a codeword that satisfies the parity check equation is generated by the LLR-BP decoding algorithm, we regard that codeword as the final estimate and halt decoding; the OSD algorithm is not performed. In this paper, we propose a new encoding/decoding scheme to lower the error floor created by irregular LDPC codes. The proposed encoding scheme encodes information bits by Cyclic Redundancy Check (CRC) and LDPC code. The proposed decoding scheme, which consists of the LLR-BP decoding, CRC check, and OSD decoding, detects errors in the codewords obtained by the LLR-BP decoding algorithm and the OSD decoding algorithm using the parity check equations of LDPC codes and CRC. Computer simulations show that the proposed encoding/decoding scheme can lower the error floor of irregular LDPC codes.

A method for constructing low-density convolutional (LDC) codes with the degree distribution optimized for block low-density parity-check (LDPC) codes is presented. If the degree distribution is irregular, the constructed LDC codes are also irregular. In this letter we give the encoding and decoding method for LDC codes, and study how to avoid the short cycles of LDC codes. Some simulation results are also presented.

In this paper we focus on the decoding error of the Log-Likelihood Ratio Belief Propagation (LLR-BP) decoding algorithm caused by oscillation. The decoding error caused by the oscillation is dominant in high Eb/N0 region. Oscillation of the LLR of the extrinsic value in the bit node process (ex-LLR) is propagated to the other bits and affects the whole decoding. The Ordered Statistic Decoding (OSD) algorithm is known to improve the error rate performance of the LLR-BP decoding algorithm. The OSD algorithm is performed by deciding the reliability of each bit based on a posteriori probability. In this paper we propose two decoding algorithms based on two types of oscillations of LLR for LDPC codes. One is the oscillation-based OSD algorithm with deciding the reliability of each bit based on oscillation. The other is the oscillation-based LLR-BP decoding algorithm that modifies ex-LLR based on oscillation. In the oscillation-based LLR-BP decoding algorithm, when ex-LLR oscillates, then we reduce the magnitude of this ex-LLR to reduce the effects on the other bits. Both algorithms improve the decoding errors caused by oscillation. From the computer simulations, we show that paying attention to the oscillation, we can improve the error rate performance of the LLR-BP decoding algorithm.

In this paper, we propose a method for constructing quasi-cyclic low-density parity-check codes randomly using cyclic shift submatrices on the basis of the girth of the Tanner graphs of these codes. We consider (3, K)-regular codes and first derive the necessary and sufficient conditions for weight-4 and weight-6 codewords to exist. On the basis of these conditions, it is possible to estimate the probability that a random method will generate a (3, K)-regular code with a minimum distance less than or equal to 6, and the proposed method is shown to offer a lower probability than does conventional random construction. Simulation results also show that it is capable of generating good codes both regular and irregular.

In this letter, we propose the Low-Density Parity-Check (LDPC) coded Orthogonal Frequency Division Multiplexing (OFDM) systems to improve the error rate performance of OFDM. We also evaluate the iterative decoding performance on both an AWGN and a frequency-selective fading channels. We show that when the energy per information bit to the noise power spectral density ratio Eb/N0 is not small, the LDPC coded OFDM (LDPC-COFDM) systems have the good error rate performance with a small number of iterations. We also show that when the Eb/N0 is small, the BER of the LDPC-COFDM systems is worse than that of the Turbo coded OFDM (TCOFDM) systems, while when the Eb/N0 is not small, the BER of the LDPC-COFDM systems is better with a small number of iterations.

Space-time transmit diversity (STTD) and space-time block coding (STBC) are attractive techniques for high bit-rate and high capacity transmission. The concatenation scheme of turbo codes and STBC (Turbo-STBC) was proposed and it has been shown that the Turbo-STBC can achieve the good error rate performance. Recently, low-density parity-check (LDPC) codes have attracted much attention as the good error correcting codes achieving the near Shannon limit performance like turbo codes. The decoding algorithm of LDPC codes has less complexity than that of turbo codes. Furthermore, when the block length is large, the error rate performance of the LDPC codes is better than that of the turbo codes with almost identical code rate and block length. In this letter, we propose a concatenation scheme of LDPC codes and STBC. We refer to it as the LDPC-STBC. We evaluate the error rate performance of the LDPC-STBC by the computer simulation and show that the error rate performance of the LDPC-STBC is almost identical to or better than that of the Turbo-STBC in a flat Rayleigh fading channel.

Richardson and Urbanke developed a powerful method density evolution which determines, for various channels, the capacity of irregular low-density parity-check code ensembles. We develop generalized density evolution for minutely represented ensembles and show it includes conventional representation as a special case. Furthermore, we present an example of code ensembles used over binary erasure channel and binary input additive white Gaussian noise channel which have better thresholds than highly optimized ensembles with conventional representation.

We propose a scheme for the design of irregular low-density parity-check (LDPC) codes based on Euclidian Geometry using Latin square matrices of random sequence. Our scheme is a deterministic method that allows the easy design of good irregular LDPC codes for any code rate and degree distribution. We optimize the LDPC codes using the Gaussian approximation method. A Euclidean Geometry LDPC code (EG-LDPC) is used as the basis for the construction of an irregular LDPC code. The base EG-LDPC code is extended by splitting rows and columns using a table of Latin square matrices of random sequence to determine the edges along which to split. We provide simulation results for codes constructed in this manner evaluated in terms of bit error rate (BER) performance in AWGN channels. We believe that our scheme is superior in terms of computational requirements and resulting BER performance in comparison to creation of irregular LDPC codes by means of random construction using a search algorithm to exclude cycles of length four.

A soft-decision decoding scheme of low-density parity-check codes (LDPC) is proposed for hard-detected signals of optical fiber communication (OFC) systems. Based on the error detection, the proposed scheme converts the received hard-decision into soft reliability for the input of the LDPC decoder, and soft-decision decoding is performed. Simulation results under OFC channels are shown and superior performance is obtained by using the proposed decoding scheme of the LDPC codes.