At present, the application of different types of memristors in electronics is being deeply studied. Given the nonlinearity characterizing memristors, a circuit with memristors cannot be treated by classical circuit analysis. In this paper, memristor is equivalent to a nonlinear dynamic system composed of linear dynamic system and nonlinear static system by Volterra series. The nonlinear transfer function of memristor is derived. In the complex frequency domain, the n-order complex frequency response of memristor is established by multiple Laplace transform, and the response of MLC parallel circuit is taken as an example to verify. Theoretical analysis shows that the complex frequency domain analysis method of memristor transforms the problem of solving nonlinear circuit in time domain into n times complex frequency domain analysis of linear circuit, which provides an idea for nonlinear dynamic system analysis.

This paper concerned the research on a memristive chaotic system and the generated random sequence; by constructing a piecewise-linear memristor model, a kind of chaotic system is constructed, and corresponding numerical simulation and dynamical analysis are carried out to show the dynamics of the new memristive chaotic system. Finally the proposed memristive chaotic system is used to generate random sequence for the possible application in encryption field.

Several new memories are being studied as candidates of future DRAM that seems difficult to be scaled. However, the read signal in these new memories needs to be amplified in a single-end manner with reference signal supplied if they are aimed for being applied to the high-density main memory. This scheme, which is fortunately not necessary in DRAM's 1/2Vdd pre-charge sense amp, can become a serious bottleneck in the new memory development, because the device electrical parameters in these new memory cells are prone to large cell-to-cell variations without exception. Furthermore, the extent to which the parameter fluctuates in data “1” is generally not the same as in data “0”. In these situations, a new sensing scheme is proposed that can minimize the sensing error rate for high-density single-end emerging memories like STT-MRAM, ReRAM and PCRAM. The scheme is based on averaging multiple dummy cell pairs that are written “1” and “0” in a weighted manner according to the fluctuation unbalance between “1” and “0”. A detailed analysis shows that this scheme is effective in designing 128Mb 1T1MTJ STT-MRAM with the results that the required TMR ratio of an MTJ can be relaxed from 130% to 90% for the fluctuation of 6% sigma-to-average ratio of MTJ resistance in a 16 pair-dummy cell averaging case by using this technology when compared with the arithmetic averaging method.

Key fabrication technology for the Pt/TiO2-x/TiO2/TiO2+x/Pt nano-film memristor is investigated, including preparing platinum (Pt) electrodes and TiO2-x/TiO2/TiO2+x nano-films. The effect of oxygen flow rate and deposition rate during fabrication on O:Ti ratio of thin films is demonstrated. The fabricated nano-films with different oxygen concentration are validated by the analyzed results from X-ray photoelectron spectroscopy (XPS). The obtained memristor device shows the typical resistive switching behavior and nonvolatile memory effects. An analytical device model for Pt/TiO2-x/TiO2/TiO2+x/Pt nano-film memristor is developed based on the fundamental linear relationships between drift-diffusion velocity and the electric field, and boundary conditions are also incorporated in this model. This model is able to predict the relation between variables in the form of explicit formula, which is very critical in memristor-based circuit designs. The measurement results from real devices validate the proposed analytical device model. Some deviations of the model from the measured data are also analyzed and discussed.

An efficient three-dimensional (3-D) fundamental locally one-dimensional finite-difference time-domain (FLOD-FDTD) method incorporated with memristor is presented. The FLOD-FDTD method achieves higher efficiency and simplicity with matrix-operator-free right-hand sides (RHS). The updating equations of memristor-incorporated FLOD-FDTD method are derived in detail. Numerical results are provided to show the trade-off between efficiency and accuracy.

In this paper, we propose a modeling approach for wireless sensor networks (WSNs) that is based on non-volatile two-dimensional cellular automata (CA) and analyze the space-time dynamics of a WSN based on the proposed model. We introduce the fourth circuit element with memory function — memristor into the cells of CA to model a non-volatile CA and employ the non-volatile CA in modeling a WSN. A state transition method is designed to implement the synchronous updates of the states between the central sensor nodes and its neighbors which might behave asynchronously in sending messages to the central one. Therefore, the energy consumption in sensor nodes can be reduced by lessening the amount of exchanged information. Simulations demonstrate that the energy consumption of a WSN can be reduced greatly based on the proposed model and the lifetime of the whole network can be increased.

This paper introduces a new hybrid CMOS-Nano circuit for efficient implementation of spiking neurons and spike-timing dependent plasticity (STDP) rule. In our spiking neural architecture, the STDP rule has been implemented by using neuron circuits which generate two-part spikes and send them in both forward and backward directions along their axons and dendrites, simultaneously. The two-part spikes form STDP windows and also they carry temporal information relating to neuronal activities. However, to reduce power consumption, we take the circuitry of two-part spike generation out of the neuron circuit and use the regular shaped pulses, after the training has been performed. Furthermore, the performance of the rule as spike-timing correlation learning and character recognition in a two layer winner-take-all (WTA) network of integrate-and-fire neurons and memristive synapses is demonstrated as a case example.

Memristor is drawing more and more attraction nowadays after HP Laboratory announced its invention. Since then many researchers are taking efforts to find its applications in various areas of the information technology. Among the important applications, one of the interesting issues is the research on memristor circuits. To put forward such research, there is an urgent demand to establish a memristor SPICE model, such that people could conduct SPICE simulation to obtain the performance of the memristor circuits under their investigation. This paper reports our efforts to meet the urgent demand. Based on the memristor device fabrication technology parameters, as well as the theoretical description on memristor, we first propose memristor SPICE models, then verify the effectiveness of the proposed models by applying it to some memristor circuits. Simulation results are satisfactory.