A practical method of measuring the contact resistance of a phosphorus-doped poly-Si plug formed on a lightly phosphorus-doped diffusion region in DRAM memory cells is described. Contact resistance was obtained electrically, using ordinary contact-chain test structures, by changing the measurement of the substrate bias. This separated the bias-dependent resistance of the lightly doped diffusion layer from the total resistance. The method was used experimentally to evaluate the feasibility of forming low-resistance contacts down to a diameter of 130 nm for giga-bit DRAMs. Electrical measurement showed that reducing the interface resistance between the poly-Si plug and the lightly doped diffusion layer was effective for forming low-resistance contacts, though a specific interface layer could not be detected by TEM observation.

A simulation model for arsenic diffusion in polycrystalline silicon has been developed considering dynamic dopant clustering and polysilicon grain growth kinetics tightly coupled with dopant diffusion and segregation. It was assumed that the polysilicon layer consists of column-like grains surrounded by thin grain-boundaries, so that one dimensional description is permissible for dopant diffusion. The dynamic clustering model was introduced for describing arsenic activation in polysilicon grains, considering the solubility limit increase for arsenic in a polysilicon. For a grain-growth calculation, a previous formula was modified to include a local concentration dependence. The simulation results show that these effects are significant for a high dose implantation case.