The electrical properties of poly-Si thin film transistors (TFTs) using rapid thermal annealing with various gate oxide thicknesses were studied in this work. It was found that Poly-Si TFT electrical characteristics with the thinnest gate oxide thickness after RTA treatment exhibits the largest performance improvement compared to TFT with thick oxide as a result of the increased incorporated amounts of the nitrogen and oxygen. Thus, the combined effects can maintain the advantages and avoid the disadvantages of scaled-down oxide, which is suitable for small-to-medium display mass production.

Diffusion of phosphorus impurities from a polycrystalline silicon films into a silicon substrate was investigated as a function of the mean concentration of phosphorus in a polycrystalline silicon film at the first diffusion stage. We presented that good control of the redistribution of implanted phosphorus impurities was possible by optimizing the normalized dose, which is the value: [the total dose of phosphorus impurities]/[the polycrystalline silicon film thickness], in the case of samples both with and without an arsenic doped layers. In the range where the normalized dose was less than 1.52.51020 cm-3, deeper junctions were formed in samples with an arsenic doped layer. In the range where the normalized dose was more than 1.52.51020 cm-3, however, deeper junctions were formed in samples without any arsenic doped layer rather than in samples with an arsenic doped layer. These results mean that formation of the junction in the device structure where a high concentration phosphorus doped polysilicon layer is stacked on to the high concentration arsenic layer embeded at the surface of the substrate can be restricted by optimizing the normalized dose. Moreover, a trade-off relationship between suppressing phosphorus diffusion and maintaining low contact resistance against normalized doses was also observed.