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[Keyword] storage class memory(6hit)

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  • Heterogeneous Integration of Precise and Approximate Storage for Error-Tolerant Workloads

    Chihiro MATSUI  Ken TAKEUCHI  

     
    PAPER

      Pubricized:
    2022/09/05
      Vol:
    E106-A No:3
      Page(s):
    491-503

    This study proposes a heterogeneous integration of precise and approximate storage in data center storage. The storage control engine allocates precise and error-tolerant applications to precise and approximate storage, respectively. The appropriate use of both precise and approximate storage is examined by applying a non-volatile memory capacity algorithm. To respond to the changes in application over time, the non-volatile memory capacity algorithm changes capacity of storage class memories (SCMs), namely the memory-type SCM (M-SCM) and storage-type SCM (S-SCM), in non-volatile memory resource. A three-dimensional triple-level cell (TLC) NAND flash is used as a large capacity memory. The results indicate that precise storage exhibits a high performance when the maximum storage cost is high. By contrast, with a low maximum storage cost, approximate storage exhibits high performance using a low bit cost approximate multiple-level cell (MLC) S-SCM.

  • Analysis on Hybrid SSD Configuration with Emerging Non-Volatile Memories Including Quadruple-Level Cell (QLC) NAND Flash Memory and Various Types of Storage Class Memories (SCMs)

    Yoshiki TAKAI  Mamoru FUKUCHI  Chihiro MATSUI  Reika KINOSHITA  Ken TAKEUCHI  

     
    PAPER-Integrated Electronics

      Vol:
    E103-C No:4
      Page(s):
    171-180

    This paper analyzes the optimal SSD configuration including emerging non-volatile memories such as quadruple-level cell (QLC) NAND flash memory [1] and storage class memories (SCMs). First, SSD performance and SSD endurance lifetime of hybrid SSD are evaluated in four configurations: 1) single-level cell (SLC)/QLC NAND flash, 2) SCM/QLC NAND flash, 3) SCM/triple-level cell (TLC)/QLC NAND flash and 4) SCM/TLC NAND flash. Furthermore, these four configurations are compared in limited cost. In case of cold workloads or high total SSD cost assumption, SCM/TLC NAND flash hybrid configuration is recommended in both SSD performance and endurance lifetime. For hot workloads with low total SSD cost assumption, however, SLC/QLC NAND flash hybrid configuration is recommended with emphasis on SSD endurance lifetime. Under the same conditions as above, SCM/TLC/QLC NAND flash tri-hybrid is the best configuration in SSD performance considering cost. In particular, for prxy_0 (write-hot workload), SCM/TLC/QLC NAND flash tri-hybrid achieves 67% higher IOPS/cost than SCM/TLC NAND flash hybrid. Moreover, the configurations with the highest IOPS/cost in each workload and cost limit are picked up and analyzed with various types of SCMs. For all cases except for the case of prxy_1 with high total SSD cost assumption, middle-end SCM (write latency: 1us, read latency: 1us) is recommended in performance considering cost. However, for prxy_1 (read-hot workload) with high total SSD cost assumption, high-end SCM (write latency: 100ns, read latency: 100ns) achieves the best performance.

  • System Performance Comparison of 3D Charge-Trap TLC NAND Flash and 2D Floating-Gate MLC NAND Flash Based SSDs

    Mamoru FUKUCHI  Chihiro MATSUI  Ken TAKEUCHI  

     
    PAPER-Integrated Electronics

      Vol:
    E103-C No:4
      Page(s):
    161-170

    This paper analyzes the system-level performance of Storage Class Memory (SCM)/NAND flash hybrid solid-state drives (SSDs) and SCM/NAND flash/NAND flash tri-hybrid SSDs in difference types of NAND flash memory. There are several types of NAND flash memory, i.e. 2-dimensional (2D) or 3-dimensional (3D), charge-trap type (CT) and floating-gate type (FG) and multi-level cell (MLC) or triple-level cell (TLC). In this paper, the following four types of NAND flash memory are analyzed: 1) 3D CT TLC, 2) 3D FG TLC, 3) 2D FG TLC, and 4) 2D FG MLC NAND flash. Regardless of read- and write-intensive workloads, SCM/NAND flash hybrid SSD with low cost 3D CT TLC NAND flash achieves the best performance that is 20% higher than that with higher cost 2D FG MLC NAND flash. The performance improvement of 3D CT TLC NAND flash can be obtained by the short write latency. On the other hand, in case of tri-hybrid SSD, SCM/3D CT TLC/3D CT TLC NAND flash tri-hybrid SSD improves the performance 102% compared to SCM/2D FG MLC/3D CT TLC NAND flash tri-hybrid SSD. In addition, SCM/2D FG MLC/2D FG MLC NAND flash tri-hybrid SSD shows 49% lower performance than SCM/2D FG MLC/3D CT TLC NAND flash tri-hybrid SSD. Tri-hybrid SSD flash with 3D CT TLC NAND flash is the best performance in tri-hybrid SSD thanks to larger block size and word-line (WL) write. Therefore, in 3D CT TLC NAND flash based SSDs, higher cost MLC NAND flash is not necessary for hybrid SSD and tri-hybrid SSD for data center applications.

  • Workload-Based Co-Design of Non-Volatile Cache Algorithm and Storage Class Memory Specifications for Storage Class Memory/NAND Flash Hybrid SSDs

    Tomoaki YAMADA  Chihiro MATSUI  Ken TAKEUCHI  

     
    PAPER

      Vol:
    E100-C No:4
      Page(s):
    373-381

    In order to realize solid-state drives (SSDs) with high performance, low energy consumption and high reliability, storage class memory (SCM)/multi-level cell (MLC) NAND flash hybrid SSD has been proposed. Algorithm of the hybrid SSD should be designed according to SCM specifications and workload characteristics. In this paper, SCMs are used as non-volatile cache. Cache operation guidelines and optimal SCM specifications for the hybrid SSD are provided for various workload characteristics. Three kinds of non-volatile cache operation for the hybrid SSD are discussed: i) write cache, ii) read-write cache without space control (RW cache) and iii) read-write cache with space control (RW cache w/ SC). SSD workloads are categorized into eight according to read/write ratio, access frequency and access data size. From evaluation result, the write cache algorithm is suitable for write-intensive workloads and read-cold-sequential workloads, while the RW cache algorithm is suitable for read-cold-random workloads to achieve the highest performance of the hybrid SSD. In contrast, as for read-hot-random workloads, write cache is appropriate when the SCM capacity is less than 3% of the NAND flash capacity. On the other hand, RW cache should be used in case that SCM capacity is more than 5% of NAND flash capacity. The effect of Memory-type SCM (M-SCM) and Storage-type SCM (S-SCM) on the hybrid SSD performance is also analyzed. The M-SCM latency is below 1 us (high speed) but the capacity is only 2% of the NAND flash capacity (small capacity). On the other hand, the S-SCM capacity is assumed to be 5% of the NAND flash capacity (large capacity) but S-SCM speed is larger than 1 us (low speed). If the additional SCM cost is limited to 20% of MLC NAND flash cost, up to 7-times and 8-times performance improvement are achieved in write-hot-random workload and read-hot-random workloads, respectively. Moreover, if the additional SCM cost is the same as MLC NAND flash cost, M-SCM/MLC NAND flash hybrid SSD achieves 24-times performance improvement.

  • NAND Phase Change Memory with Block Erase Architecture and Pass-Transistor Design Requirements for Write and Disturbance

    Koh JOHGUCHI  Kasuaki YOSHIOKA  Ken TAKEUCHI  

     
    PAPER

      Vol:
    E97-C No:4
      Page(s):
    351-359

    In this paper, we propose an optimum access method for a phase change memory (PCM) with NAND strings. A PCM with a block erase interface is proposed. The method, which has a SET block erase operation and fast RESET programming, is proposed since the SET operation causes a slow access time for conventional PCM;. From the results of measurement, the SET-ERASE operation is successfully completed while the RESET-ERASE operation is incomplete owing to serial connection. As a result, the block erase interface with the SET-ERASE and RESET program method realizes a 7.7 times faster write speed compared than a conventional RAM interface owing to the long SET time. We also give pass-transistor design guidelines for PCM with NAND strings. In addition, the write-capability and write-disturb problems are investigated. The ERASE operation for the proposed device structure can be realized with the same current as that for the SET operation of a single cell. For the pass transistor, about 4.4 times larger on-current is needed to carry out the RESET operation and to avoid the write-disturb problem than the minimum RESET current of a single cell. In this paper, the SET programming method is also verified for a conventional RAM interface. The experimental results show that the write-capability and write-disturb problems are negligible.

  • Performance and Energy Efficiency Tradeoffs of Storage Class Memory

    Heekwon PARK  Seungjae BAEK  Jongmoo CHOI  

     
    LETTER-Computer System

      Vol:
    E93-D No:11
      Page(s):
    3112-3115

    The traditional mobile consumer electronics such as media players and smart phones use two distinct memories, SDRAM and Flash memory. SDRAM is used as main memory since it has characteristic of byte-unit random accessibility while Flash memory as secondary storage due to its characteristic of non-volatility. However, the advent of Storage Class Memory (SCM) that supports both SDRAM and Flash memory characteristics gives an opportunity to design a new system configuration. In this paper, we explore four feasible system configurations, namely RAM-Flash, RAM-SCM, SCM-Flash and SCM-Only. Then, using a real embedded system equipped with FeRAM, a type of SCM, we analyze the tradeoffs between performance and energy efficiency of each configuration. Experimental results have shown that SCM has great potential to reduce energy consumption for all configurations while performance is highly application dependent and might be degraded on the SCM-Flash and SCM-Only configuration.