In order to improve the forward link capacity of cdma2000 HRPD (High Rate Packet Data) or CDMA2000 1xEV-DO, it is significant to overcome multi-path interference. This paper focuses on FDE (Frequency Domain Equalization) with MMSE (Minimum Mean Square Error) criterion. On top of that, backward compatibility with HRPD should be maintained, in other words common channels such as the pilot channel should not be changed. Thus, the PN (Pseudo Noise) spread pilot block without CP (Cyclic Prefix) signals has to be dealt with for FDE. However, this will cause the conventional channel estimation accuracy to deteriorate. In order to improve the estimation accuracy of the conventional method, this paper presents a MRC (Maximal Ratio Combining) spectrum estimator, IPI (Inter-Path Interference) canceller, and path searcher. The results obtained from computer simulations reveal that the proposed method can improve the PER (Packet Error Rate) performance significantly. If compared with Rake combiner and TDE (Time Domain Equalization) with NLMS (Normalized Least Mean Square) scheme, the maximum data rates at a fixed PER of 1% can be increased by 5 to 8 times and 1.25 to 2.67 times, respectively.

A time-domain equalization (TEQ) algorithm is presented to shorten the effective channel impulse response to increase the transmission efficiency of the 54 Mbps IEEE 802.11a orthogonal frequency division multiplexing (OFDM) system. In solving the linear equation Aw = B for the optimum TEQ coefficients, A is shown to be Hermitian and positive definite. The LDLT and LU decompositions are used to factorize A to reduce the computational complexity. Simulation results show high performance gains at a data rate of 54 Mbps with moderate orders of TEQ finite impulse response (FIR) filter. The design and implementation of the algorithm in field programmable gate array (FPGA) are also presented. The regularities among the elements of A are exploited to reduce hardware complexity. The LDLT and LU decompositions are combined in hardware design to find the TEQ coefficients in less than 4 µs. To compensate the effective channel impulse response, a radix-4 pipeline fast Fourier transform (FFT) is implemented in performing zero forcing equalization. The hardware implementation information is provided and simulation results are compared to mathematical values to verify the functionalities of the chips running at 54 Mbps.