IEICE TRANSACTIONS on Electronics
A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI
Summary :
We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2 Mb test device has been fabricated on 130 nm SOI-CMOS process. We demonstrate the TTRAM cell has two data-storage states and confirm the data retention time of 100 ms at 80
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.4 pp.765-771
- Publication Date
- 2007/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.4.765
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
- Category
- Memory
Authors
Fukashi MORISHITA
Hideyuki NODA
Isamu HAYASHI
Takayuki GYOHTEN
Mako OKAMOTO
Takashi IPPOSHI
Shigeto MAEGAWA
Katsumi DOSAKA
Kazutami ARIMOTO
Keyword
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Fukashi MORISHITA, Hideyuki NODA, Isamu HAYASHI, Takayuki GYOHTEN, Mako OKAMOTO, Takashi IPPOSHI, Shigeto MAEGAWA, Katsumi DOSAKA, Kazutami ARIMOTO, "A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 4, pp. 765-771, April 2007, doi: 10.1093/ietele/e90-c.4.765.
Abstract: We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2 Mb test device has been fabricated on 130 nm SOI-CMOS process. We demonstrate the TTRAM cell has two data-storage states and confirm the data retention time of 100 ms at 80
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.4.765/_p
Copy
@ARTICLE{e90-c_4_765,
author={Fukashi MORISHITA, Hideyuki NODA, Isamu HAYASHI, Takayuki GYOHTEN, Mako OKAMOTO, Takashi IPPOSHI, Shigeto MAEGAWA, Katsumi DOSAKA, Kazutami ARIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI},
year={2007},
volume={E90-C},
number={4},
pages={765-771},
abstract={We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2 Mb test device has been fabricated on 130 nm SOI-CMOS process. We demonstrate the TTRAM cell has two data-storage states and confirm the data retention time of 100 ms at 80
keywords={},
doi={10.1093/ietele/e90-c.4.765},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI
T2 - IEICE TRANSACTIONS on Electronics
SP - 765
EP - 771
AU - Fukashi MORISHITA
AU - Hideyuki NODA
AU - Isamu HAYASHI
AU - Takayuki GYOHTEN
AU - Mako OKAMOTO
AU - Takashi IPPOSHI
AU - Shigeto MAEGAWA
AU - Katsumi DOSAKA
AU - Kazutami ARIMOTO
PY - 2007
DO - 10.1093/ietele/e90-c.4.765
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2007
AB - We propose a novel capacitorless twin-transistor random access memory (TTRAM). The 2 Mb test device has been fabricated on 130 nm SOI-CMOS process. We demonstrate the TTRAM cell has two data-storage states and confirm the data retention time of 100 ms at 80
ER -
English
