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An analytical model of the static noise margin (SNM) for a 6T CMOS SRAM suitable for use in investigating the effect of random *V*_{th} variation is derived. A three-step approach using characteristic points of the half cell inverter's transfer curve is developed. Parameters of each transistor are handled individually so that their sensitivities are calculable. A new MOSFET model in the moderate inversion is proposed to maintain accuracy, even in the low *V*_{DD} condition. Correlation between the proposed model calculations and circuit simulations was verified using a 90 nm CMOS LSTP device. Closely correlated dependency on parameters such as *V*_{th}, the *W* ratio, and *V*_{DD} were obtained. Maximum error measured in the *V*_{DD} range of 0.6-1.6 V was 16 mV (7% of typical SNM). Finally, guidelines to obtain large SNM are discussed in this paper.

- Publication
- IEICE TRANSACTIONS on Electronics Vol.E91-C No.9 pp.1488-1500

- Publication Date
- 2008/09/01

- Publicized

- Online ISSN
- 1745-1353

- DOI
- 10.1093/ietele/e91-c.9.1488

- Type of Manuscript
- PAPER

- Category
- Electronic Circuits

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Hirofumi SHINOHARA, Koji NII, Hidetoshi ONODERA, "Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 9, pp. 1488-1500, September 2008, doi: 10.1093/ietele/e91-c.9.1488.

Abstract: An analytical model of the static noise margin (SNM) for a 6T CMOS SRAM suitable for use in investigating the effect of random *V*_{th} variation is derived. A three-step approach using characteristic points of the half cell inverter's transfer curve is developed. Parameters of each transistor are handled individually so that their sensitivities are calculable. A new MOSFET model in the moderate inversion is proposed to maintain accuracy, even in the low *V*_{DD} condition. Correlation between the proposed model calculations and circuit simulations was verified using a 90 nm CMOS LSTP device. Closely correlated dependency on parameters such as *V*_{th}, the *W* ratio, and *V*_{DD} were obtained. Maximum error measured in the *V*_{DD} range of 0.6-1.6 V was 16 mV (7% of typical SNM). Finally, guidelines to obtain large SNM are discussed in this paper.

URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.9.1488/_p

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@ARTICLE{e91-c_9_1488,

author={Hirofumi SHINOHARA, Koji NII, Hidetoshi ONODERA, },

journal={IEICE TRANSACTIONS on Electronics},

title={Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration},

year={2008},

volume={E91-C},

number={9},

pages={1488-1500},

abstract={An analytical model of the static noise margin (SNM) for a 6T CMOS SRAM suitable for use in investigating the effect of random *V*_{th} variation is derived. A three-step approach using characteristic points of the half cell inverter's transfer curve is developed. Parameters of each transistor are handled individually so that their sensitivities are calculable. A new MOSFET model in the moderate inversion is proposed to maintain accuracy, even in the low *V*_{DD} condition. Correlation between the proposed model calculations and circuit simulations was verified using a 90 nm CMOS LSTP device. Closely correlated dependency on parameters such as *V*_{th}, the *W* ratio, and *V*_{DD} were obtained. Maximum error measured in the *V*_{DD} range of 0.6-1.6 V was 16 mV (7% of typical SNM). Finally, guidelines to obtain large SNM are discussed in this paper.},

keywords={},

doi={10.1093/ietele/e91-c.9.1488},

ISSN={1745-1353},

month={September},}

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TY - JOUR

TI - Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration

T2 - IEICE TRANSACTIONS on Electronics

SP - 1488

EP - 1500

AU - Hirofumi SHINOHARA

AU - Koji NII

AU - Hidetoshi ONODERA

PY - 2008

DO - 10.1093/ietele/e91-c.9.1488

JO - IEICE TRANSACTIONS on Electronics

SN - 1745-1353

VL - E91-C

IS - 9

JA - IEICE TRANSACTIONS on Electronics

Y1 - September 2008

AB - An analytical model of the static noise margin (SNM) for a 6T CMOS SRAM suitable for use in investigating the effect of random *V*_{th} variation is derived. A three-step approach using characteristic points of the half cell inverter's transfer curve is developed. Parameters of each transistor are handled individually so that their sensitivities are calculable. A new MOSFET model in the moderate inversion is proposed to maintain accuracy, even in the low *V*_{DD} condition. Correlation between the proposed model calculations and circuit simulations was verified using a 90 nm CMOS LSTP device. Closely correlated dependency on parameters such as *V*_{th}, the *W* ratio, and *V*_{DD} were obtained. Maximum error measured in the *V*_{DD} range of 0.6-1.6 V was 16 mV (7% of typical SNM). Finally, guidelines to obtain large SNM are discussed in this paper.

ER -