Design Methodology of Deep Submicron CMOS Devices for 1 V Operation

Hisato OYAMATSU; Masaaki KINUGAWA; Masakazu KAKUMU

Design Methodology of Deep Submicron CMOS Devices for 1 V Operation

Hisato OYAMATSU, Masaaki KINUGAWA, Masakazu KAKUMU

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A design methodology of high performance deep submicron CMOS in very low voltage operation has been proposed from low power dissipation point of view. In low voltage operation, threshold voltage is restricted by performance, stability of CMOS circuits and power dissipation caused by standby and switching transient current. As a result, threshold voltage is established to be 0.15 V even at 1 V operation from these requirements. Moreover, according to this design, 0.15 µm CMOS was fabricated with reduction of parasitic effects. It achieved propagation delay time 50 psec at 1 V operation. This results confirms that this design methodology is promising to achieve high performance deep submicron CMOS devices for low power dissipation.

Publication: IEICE TRANSACTIONS on Electronics Vol.E79-C No.12 pp.1720-1725

Publication Date: 1996/12/25

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Type of Manuscript: Special Section PAPER (Special Issue on Low-Power LSI Technologies)

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Hisato OYAMATSU, Masaaki KINUGAWA, Masakazu KAKUMU, "Design Methodology of Deep Submicron CMOS Devices for 1 V Operation" in IEICE TRANSACTIONS on Electronics, vol. E79-C, no. 12, pp. 1720-1725, December 1996, doi: .
Abstract: A design methodology of high performance deep submicron CMOS in very low voltage operation has been proposed from low power dissipation point of view. In low voltage operation, threshold voltage is restricted by performance, stability of CMOS circuits and power dissipation caused by standby and switching transient current. As a result, threshold voltage is established to be 0.15 V even at 1 V operation from these requirements. Moreover, according to this design, 0.15 µm CMOS was fabricated with reduction of parasitic effects. It achieved propagation delay time 50 psec at 1 V operation. This results confirms that this design methodology is promising to achieve high performance deep submicron CMOS devices for low power dissipation.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_12_1720/_p

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@ARTICLE{e79-c_12_1720,
author={Hisato OYAMATSU, Masaaki KINUGAWA, Masakazu KAKUMU, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design Methodology of Deep Submicron CMOS Devices for 1 V Operation},
year={1996},
volume={E79-C},
number={12},
pages={1720-1725},
abstract={A design methodology of high performance deep submicron CMOS in very low voltage operation has been proposed from low power dissipation point of view. In low voltage operation, threshold voltage is restricted by performance, stability of CMOS circuits and power dissipation caused by standby and switching transient current. As a result, threshold voltage is established to be 0.15 V even at 1 V operation from these requirements. Moreover, according to this design, 0.15 µm CMOS was fabricated with reduction of parasitic effects. It achieved propagation delay time 50 psec at 1 V operation. This results confirms that this design methodology is promising to achieve high performance deep submicron CMOS devices for low power dissipation.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - Design Methodology of Deep Submicron CMOS Devices for 1 V Operation
T2 - IEICE TRANSACTIONS on Electronics
SP - 1720
EP - 1725
AU - Hisato OYAMATSU
AU - Masaaki KINUGAWA
AU - Masakazu KAKUMU
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1996
AB - A design methodology of high performance deep submicron CMOS in very low voltage operation has been proposed from low power dissipation point of view. In low voltage operation, threshold voltage is restricted by performance, stability of CMOS circuits and power dissipation caused by standby and switching transient current. As a result, threshold voltage is established to be 0.15 V even at 1 V operation from these requirements. Moreover, according to this design, 0.15 µm CMOS was fabricated with reduction of parasitic effects. It achieved propagation delay time 50 psec at 1 V operation. This results confirms that this design methodology is promising to achieve high performance deep submicron CMOS devices for low power dissipation.
ER -