A 1-V MTCMOS Circuit Hardened to Temperature-Dependent Delay-Time Variation
Summary :
This paper describes the effects of operating temperature on delay time in a 1-V multi-threshold CMOS(MTCMOS) circuit, Delay-time analysis including the temperature factor shows that the delay-time variation of the CMOS circuit becomes amall for low-voltage operation and the variation is mainly determined by the threshold voltage and its variation-rate with temperature. As a design method of a MTCMOS circuit with both high-threshold and low-threshold MOSFETs, optimization of the low-threshold voltage at which the delay-time of the circuit is independent of operating temperature is described in detail. The validity of the design method is confirmed by the evaluation of a gate-chain TEG and a 1-V 12 K-gate digital-filter LSI fabricated with o.5-µm MTCMOS technology.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E79-C No.8 pp.1131-1136
- Publication Date
- 1996/08/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
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Takakuni DOUSEKI, Shin-ichiro MUTOH, "A 1-V MTCMOS Circuit Hardened to Temperature-Dependent Delay-Time Variation" in IEICE TRANSACTIONS on Electronics,
vol. E79-C, no. 8, pp. 1131-1136, August 1996, doi: .
Abstract: This paper describes the effects of operating temperature on delay time in a 1-V multi-threshold CMOS(MTCMOS) circuit, Delay-time analysis including the temperature factor shows that the delay-time variation of the CMOS circuit becomes amall for low-voltage operation and the variation is mainly determined by the threshold voltage and its variation-rate with temperature. As a design method of a MTCMOS circuit with both high-threshold and low-threshold MOSFETs, optimization of the low-threshold voltage at which the delay-time of the circuit is independent of operating temperature is described in detail. The validity of the design method is confirmed by the evaluation of a gate-chain TEG and a 1-V 12 K-gate digital-filter LSI fabricated with o.5-µm MTCMOS technology.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_8_1131/_p
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@ARTICLE{e79-c_8_1131,
author={Takakuni DOUSEKI, Shin-ichiro MUTOH, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 1-V MTCMOS Circuit Hardened to Temperature-Dependent Delay-Time Variation},
year={1996},
volume={E79-C},
number={8},
pages={1131-1136},
abstract={This paper describes the effects of operating temperature on delay time in a 1-V multi-threshold CMOS(MTCMOS) circuit, Delay-time analysis including the temperature factor shows that the delay-time variation of the CMOS circuit becomes amall for low-voltage operation and the variation is mainly determined by the threshold voltage and its variation-rate with temperature. As a design method of a MTCMOS circuit with both high-threshold and low-threshold MOSFETs, optimization of the low-threshold voltage at which the delay-time of the circuit is independent of operating temperature is described in detail. The validity of the design method is confirmed by the evaluation of a gate-chain TEG and a 1-V 12 K-gate digital-filter LSI fabricated with o.5-µm MTCMOS technology.},
keywords={},
doi={},
ISSN={},
month={August},}
Copy
TY - JOUR
TI - A 1-V MTCMOS Circuit Hardened to Temperature-Dependent Delay-Time Variation
T2 - IEICE TRANSACTIONS on Electronics
SP - 1131
EP - 1136
AU - Takakuni DOUSEKI
AU - Shin-ichiro MUTOH
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 1996
AB - This paper describes the effects of operating temperature on delay time in a 1-V multi-threshold CMOS(MTCMOS) circuit, Delay-time analysis including the temperature factor shows that the delay-time variation of the CMOS circuit becomes amall for low-voltage operation and the variation is mainly determined by the threshold voltage and its variation-rate with temperature. As a design method of a MTCMOS circuit with both high-threshold and low-threshold MOSFETs, optimization of the low-threshold voltage at which the delay-time of the circuit is independent of operating temperature is described in detail. The validity of the design method is confirmed by the evaluation of a gate-chain TEG and a 1-V 12 K-gate digital-filter LSI fabricated with o.5-µm MTCMOS technology.
ER -
English
