A 5.8 ns 256 kb SRAM with 0.4 µm Super-CMOS Process Technology

Kunihiko KOZARU; Atsushi KINOSHITA; Tomohisa WADA; Yutaka ARITA; Michihiro YAMADA

A 5.8 ns 256 kb SRAM with 0.4 µm Super-CMOS Process Technology

Kunihiko KOZARU, Atsushi KINOSHITA, Tomohisa WADA, Yutaka ARITA, Michihiro YAMADA

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This paper presents Super-CMOS SRAM process technology that integrates bipolar and CMOS transistors in a chip while adding only one ion implantation step and no lithography mask steps to the conventional CMOS SRAM process. The Super-CMOS SRAM process therefore has the same process cost as the CMOS SRAMs, while it achieves higher access speeds. In order to demonstrate the Super-CMOS SRAM, we have developed a 3.3 V/5 V 256 kb SRAM using 0.4 µm Super-CMOS process technology. By applying bipolar transistors to the sense amplifier circuits, a high-speed access time of 5.8 ns with a 3.0 V power supply is successfully achieved.

Publication: IEICE TRANSACTIONS on Electronics Vol.E80-C No.4 pp.566-572

Publication Date: 1997/04/25

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Type of Manuscript: Special Section PAPER (Special Issue on Circuit Technologies for Memory and Analog LSIs)

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Kunihiko KOZARU, Atsushi KINOSHITA, Tomohisa WADA, Yutaka ARITA, Michihiro YAMADA, "A 5.8 ns 256 kb SRAM with 0.4 µm Super-CMOS Process Technology" in IEICE TRANSACTIONS on Electronics, vol. E80-C, no. 4, pp. 566-572, April 1997, doi: .
Abstract: This paper presents Super-CMOS SRAM process technology that integrates bipolar and CMOS transistors in a chip while adding only one ion implantation step and no lithography mask steps to the conventional CMOS SRAM process. The Super-CMOS SRAM process therefore has the same process cost as the CMOS SRAMs, while it achieves higher access speeds. In order to demonstrate the Super-CMOS SRAM, we have developed a 3.3 V/5 V 256 kb SRAM using 0.4 µm Super-CMOS process technology. By applying bipolar transistors to the sense amplifier circuits, a high-speed access time of 5.8 ns with a 3.0 V power supply is successfully achieved.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e80-c_4_566/_p

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@ARTICLE{e80-c_4_566,
author={Kunihiko KOZARU, Atsushi KINOSHITA, Tomohisa WADA, Yutaka ARITA, Michihiro YAMADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 5.8 ns 256 kb SRAM with 0.4 µm Super-CMOS Process Technology},
year={1997},
volume={E80-C},
number={4},
pages={566-572},
abstract={This paper presents Super-CMOS SRAM process technology that integrates bipolar and CMOS transistors in a chip while adding only one ion implantation step and no lithography mask steps to the conventional CMOS SRAM process. The Super-CMOS SRAM process therefore has the same process cost as the CMOS SRAMs, while it achieves higher access speeds. In order to demonstrate the Super-CMOS SRAM, we have developed a 3.3 V/5 V 256 kb SRAM using 0.4 µm Super-CMOS process technology. By applying bipolar transistors to the sense amplifier circuits, a high-speed access time of 5.8 ns with a 3.0 V power supply is successfully achieved.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - A 5.8 ns 256 kb SRAM with 0.4 µm Super-CMOS Process Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 566
EP - 572
AU - Kunihiko KOZARU
AU - Atsushi KINOSHITA
AU - Tomohisa WADA
AU - Yutaka ARITA
AU - Michihiro YAMADA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 1997
AB - This paper presents Super-CMOS SRAM process technology that integrates bipolar and CMOS transistors in a chip while adding only one ion implantation step and no lithography mask steps to the conventional CMOS SRAM process. The Super-CMOS SRAM process therefore has the same process cost as the CMOS SRAMs, while it achieves higher access speeds. In order to demonstrate the Super-CMOS SRAM, we have developed a 3.3 V/5 V 256 kb SRAM using 0.4 µm Super-CMOS process technology. By applying bipolar transistors to the sense amplifier circuits, a high-speed access time of 5.8 ns with a 3.0 V power supply is successfully achieved.
ER -